Abstract
With transistor dimension shrinking into nanoscale regime, it suffers from significant drive current reduction, due to mobility degradation and source/drain parasitic resistance increase. The big challenge going forward is that continued scaling of Si transistors will be more and more difficult because of both fundamental limitations and practical considerations as the transistor dimension approach 7 nm. Low-resistivity self-aligned metal source/drain is a very promising approach for solving these mentioned problems in source/drain engineering. Therefore, this thesis focuses on the source/drain engineering of nMOSFETs and several feasible solutions have been proposed. First, Ti is proposed to modulate the electron Schottky barrier height with RE metal confinement structure in p-Si (100) substrates, and extremely low electron SBH is achieved with optimized process parameters. By inserting a Ti diffusion barrier between Yb and Ni layers, the Yb atoms are constrained in a specified reaction region for silicidation. Moreover, the Schottky barrier height modulations (ΔΦB) of the Yb-Ni-silicide diode using confinement structure are 0.02 and 0.025 eV at an annealing temperature of 500 and 600 oC, respectively. The feasibility of the confinement structure in nMOSFET application is also demonstrated in this work. Second, we have demonstrated that the RE metal confinement structure can also be successfully applied to the III-V (GaAs) substrate. Finally, the material and electrical properties of the Yb, Ni, Ge ohmic contact metallization for GaAs and InGaAs substrate have been extensively explored, which is very beneficial for the performance improvement on III–V n-MOSFETs.