Abstract
Due to the advanced VLSI technology process, the transistor count in a single IC continues to grow so that more complex and powerful devices can be manufactured within small areas. Furthermore, the modern integration technology such as system in package (SIP) and through silicon via (TSV) provides a good ability to integrate heterogeneous devices within the same chip. Based on these technologies, the circuit and system performance can be greatly improved. However, these technologies also bring some challenges. Since more and more devices (transistors) are placed in a given area, the power density of chip is also increased. This effect severely results the thermal problem which can degrade the system reliability and performance. Moreover, increasing the number of device in a single IC needs the additional power budget. To alleviate the power wall, the device management is required to achieve high performance and low energy consumption system. In this dissertation, the exploration of cache architecture and design optimization techniques are proposed to improve system performance, power, and thermal issues in system and physical design levels. First, in physical design level, a study of stacked signal TSV for thermal dissipation in global routing for 3D IC is introduced. Stacked TSV structure proposed by Chen et al. is very efficiency in dissipating the heat flow for 3D. However, the original stacked TSV structure is only used in power network. In this work, we leverage the integrated architecture of stacked signal TSV to minimize temperature with small wiring overhead. Based on the structure of stacked signal TSV, a three-stage TSV locating algorithm in global routing is designed. Second, in system design level, a study of thread-criticality aware dynamic cache reconfiguration for multi-core system is proposed. Reconfigurable cache proposed by Zhang et al. can improve system performance and energy consumption. However, the original reconfigurable cache only used in single core system. In this work, we dynamically predict thread criticality of a parallel application and tune our cache memory architecture accordingly in multi-core system. Finally, a study of compaction-free compressed cache for high performance multi-core system is introduced. Compressed cache is usually used in last level cache to increase the effective capacity. However, because of various data compression sizes, fragmentation problem of storage is inevitable in this cache design. When it happens, usually, a compaction process is invoked to make contiguous storage space. This compaction process induces extra cycle penalty and degrades the effectiveness of compressed cache design. In this work, we propose a compaction-free compressed cache architecture which can completely eliminate the time for executing compaction.