Abstract
The wafer bonding technique was applied in this paper to enhance the light extraction efficiency and thermal performance of AlGaInP light-emitting diodes (LEDs). This technique can replace the GaAs substrate with other high thermal conductivity substrates. However, it can make the film crack either during the removal etching process of the GaAs substrate or the annealing process after the GaAs’ removal. Therefore, this crack problem is an important reliability/yield issue of high-brightness LEDs during their manufacturing process. The material properties of a film and substrate, such as Young’s modulus, lattice parameters, and CTE, vary. Residual stress can also build up during fabrication and processing. Therefore, the resultant stresses inside the film and substrate can be different as well and cause a deflection of the composite structure to increase or relax stress. Therefore, the workability of theories used to calculate thermal stresses in thin films are first discussed and examined using finite element analysis (FEA). When the substrate curvature is in a small deformation range, the prediction results of the in-plane stress of a film by using these equations are similar to the trend exhibited by FEA. However, the detailed stress distributions change with each process. Deposition, etching, and wafer bonding within a material cannot be determined using these multilayer theories. Hence, this research proposes a novel simulation method that combines process modelling, bonding contact technique and the modified virtual crack closure technique (MVCCT) to understand the mechanical behavior of high-brightness AlGaInP LEDs during the fabrication process. After validating the above simulation techniques through several simple experiments, the simplified 2D finite element model of a multilayer LED structure is established and examined. According to the simulation results, the concentrated stress occurs near the step coverage range, and this stress is increased significantly when the structural and loading temperature is raised to a high level. These highly concentrated stresses may induce cracks in the brittle layers and weak interface. The results of the parametric study also provide a design guideline to reduce the concentrated stresses. If the step coverage range can be removed, the above concentrated stresses produced by the geometry effect can be eliminated. The foregoing design guideline is also validated and examined using FEA and test samples fabrication, respectively. Overall, the proposed methodologies in this research can be used to help eliminate crack problems and enhance the reliability of fabrication for semiconductor manufacture.