Abstract
This thesis focuses on the the process fully compatible with incumbent ultra-large-scale integration (ULSI) technology, and hence, providing an economic way of fabricating high-performance Ge MOSFETs without using a Ge substrate and how to solve issues on Ge bulk device integration. We concentrate the most critical issue which obtains a high-quality interface between Ge and the high-κ dielectric. Crystalline high-κ materials were introduced to replace amorphous dielectric, since they can offer a larger physical thickness while maintaining a low EOT due to their higher κ value. First, Metal-oxide-semiconductor (MOS) devices, using a Si substrate and a thermal SiON film as the gate dielectric on a Ge layer, have been physically and electrically characterized. The small frequency dispersion and negligible hysteresis demonstrate very few oxide traps. The efficiency of Ge surface passivation is evidenced by the acceptable interface trap density of 7.08 ×1011 cm-2 eV-1 close to midgap, which is critical for the enhancement of the carrier mobility in MOSFET devices. On the other hand, for the thermal SiON film, a higher permittivity of 4.86 can be achieved by NH3 nitridation and a subsequent N2O treatment of an as-grown SiO2 film without compromising its leakage current. The conduction mechanism is confirmed to be Fowler-Nordheim (F-N) tunneling with extracted electron barrier height of 2.71 eV. Combining with these promising properties, the SiON film shows a great potential to further boost the performance of Ge MOSFETs. Next, a Ge-stabilized tetragonal ZrO2 (t-ZrO2) film formed by incorporating Ge atoms thermally driven from an underlying Ge layer into a ZrO2 film was investigated as the gate dielectric for Ge MOS capacitors fabricated on a Si substrate. By using a thermally-grown ultrathin GeO2 film as an interfacial layer, the t-ZrO2/GeO2/Ge stack shows improved interface characteristics and a κ value of 36.6 for the t-ZrO2. Further leakage current suppression can be achieved by a H2 annealing of the t-ZrO2/GeO2/Ge stack, which makes a paves an alternative avenue to develop a high-performance crystalline gate dielectric for Ge MOS devices. Besides, in order to improve dielectric constant and thermal stability of interface layer, we demonstrate GeOx-based material to enhance interface quality and characteristic. The first material, SnGeOx films formed by thermal oxidation of Sn/Ge and SnGex/Ge structures were explored to investigate the capability of passivation for Ge MOS devices. It is found that Sn incorporation into germanium oxide is effective in suppressing the formation of volatile GeO. Furthermore, the films also demonstrate desirable electrical characteristics in terms of tiny frequency dispersion and small hysteresis in capacitance measurement. The second material, YGeOx formed by thermal oxidation of Y/Ge structure was to investigate the capability of passivation for Ge MOS devices. Because of the thermal oxidation nature of the process that effectively suppresses dielectric structural defects and incorporates sufficient Y atoms at the interface to well passivate the dangling bonds on Ge surface, the YGeOx enjoys a small amount of oxide traps and a low interface trap density (Dit) of 2.1×1011 cm−2 eV−1. In addition, the thermally grown YGeOx demonstrates a relatively high dielectric constant of 10.8 as compared to GeO2, tiny frequency dispersion in C-V characteristics Finally, rare-earth oxide material is investigated as passivation layer in Ge MOS capacitors with crystalline high-κ gate dielectric. The first stack, by adopting an amorphous Y2O3 passivation layer, which provides a wide band gap and well passivates Ge surface without the presence of GeOx, a high-κ crystalline ZrO2/Y2O3 stack was explored as the gate dielectric for Ge MOS devices on Si substrate. The crystalline ZrO2 is a Ge stabilized tetragonal/cubic dielectric with the κ value of 36.1 and was formed by depositing a ZrO2/Ge/ZrO2 laminate and a subsequent 500 °C annealing. The high-κ crystalline ZrO2/Y2O3 gate stack shows promising electrical characteristics in terms of low Dit of 5.8×1011 cm−2 eV−1, negligible hysteresis. The second stack, by adopting an amorphous Yb2O3 passivation layer, which provides a large conduction band offset and well passivates Ge surface, a high-κ crystalline ZrTiO4/Yb2O3 stack was explored as the gate dielectric for Ge MOS devices. With 600 ◦C annealing, the ZrTiO4 film can be crystallized in orthorhombic phase and orthorhombic-ZrTiO4 enjoys an even higher κ value of 43.2. This crystalline ZrTiO4/Yb2O3 gate stack demonstrates EOT of 0.76 nm, desirable Dit of 7.8 × 1011 cm−2eV−1, and good leakage current. Therefore, the stack demonstrates good performance characteristics.