Abstract
Two dimensional (2D) materials are drawing growing attention for next-generation electronics and optoelectronics owing to its atomic thin layer and unique physical properties. One of the challenges posed by 2D materials for transistor applications is the large source/drain (S/D) series resistance due to their thinness, which may be resolved by thickening the source and drain regions. Recently explored lateral graphene−MoS2 and graphene−WS2 heterostructures shed light on resolving this issue owing to their superior ohmic contact behaviors. However, recently only n-type field-effect transistors (FETs) are reported for transistors with graphene-TMD heterostructures. The lack of p-type transistor limits their applications in complementary metal-oxide semiconductor (CMOS) electronics. In this dissertation, we devote on demonstrating p-type FETs based on graphene-WSe2 lateral heterojunctions grown with the scalable CVD technique. Few-layer WSe2 is overlapped with the multilayer graphene (MLG) at MLG-WSe2 junctions such that the contact resistance is reduced drastically. Importantly, the few-layer WSe2 only forms at the junction region while the channel is still maintained as a WSe2 monolayer for transistors operation. Furthermore, by imposing doping to graphene S/D, two orders of magnitude enhancement in Ion/Ioff ratio to ~108 and the unipolar p-type characteristics are obtained regardless the work function of the metal in ambient air condition. The MLG is proposed to serve for a 2D version of emerging raised source/drain (RSD) approach in electronics.