Abstract
The quest for technologies beyond the 10 nm node CMOS has now driven efforts in fabricating inversion-channel III-V MOSFETs with high κ dielectrics, owing to the high electron mobility in GaAs-based materials. One of the most challenging issues for realizing the high-performance GaAs-based inversion-channel MOSFETs is to decrease the parasitic series resistance, of which the contact resistance is the dominant component in the highly scaled devices. In this dissertation, we demonstrate the device performance of a 4- μm-gate-length self-aligned inversion-channel In0.2Ga0.8As MOSFET on GaAs (100) substrate using a gate dielectric of Al2O3 (3 nm thick)/GGO (8 nm thick) with a maximum drain current of 9.5 μA/μm, and an extrinsic maximum transconductance of 3.9 μS/μm. The device performances are compared favorably with those of other inversion-channel GaAs MOSFETs on GaAs (100), and also of the device on GaAs (111)A substrates using atomic layer deposited (ALD) Al2O3 as a gate dielectric. Except for the In0.2Ga0.8As inversion-channel MOSFETs, non-gold ohmic contacts of Pd/Ge/Ti/Pt have been investigated on highly doped molecular beam epitaxy (MBE) grown GaAs, In0.2Ga0.8As and In0.53Ga0.47As epilayers and a low contact resistance of 1×10-7 Ω-cm2 has been achevied on In0.53Ga0.47As, as a feasibility assessment in using these semiconductors for the post Si CMOS. In addition, high thermal stability (~900 ºC) TiN dual metal gate has been obtained by inserting an ALD-TiN layer between gate dielectric and sputtered-TiN, which is very promising for applying to self-aligned inversion-channel GaAs-based MOSFETs.