Abstract
As the advance of the CMOS process and electronic design automation (EDA) technology, the SoC design becomes more and more practical and popular. Various individual IPs are integrated together into a single chip to achieve lower area, lower power and higher speed design. However, a lot of parallel lines communicate between heterogeneous IPs. It will be marked as routing overhead, large capacitive load, large power consumption, large area and propagation delay overhead. However, the power consumption will increase when multiplexing parallel bus into a serial link. Therefore, we propose an embedded transition inversion (ETI) coding to reduce the power consumption of serial link without extra bit in the codeword to avoid the latency problem in other coding schemes. In addition, we propose a selective spacing (SS) method to choose the minimum parasitic capacitance and area consumption for different value of multiplexing. This ETI coding scheme reduces the transition by up to 31% compared with the encoding followed by serial (ES) scheme. For analysis and simulation results, this study indicates that the proposed coding scheme produces a low bit transition for different kinds of data patterns. Using the optimum degree of multiplexing, optimum width and spacing, the bus energy dissipation can be minimized. Using these optimum parameters, the ETI coding scheme achieves 30% to 70% less energy compared with the parallel bus. The higher operating frequency will decrease the timing margin for high-performance SoC systems. As the timing margin is tight, the timing skews and jitters would make it difficult to synchronize among IC modules. Delay locked loops (DLL) has been typically employed for purpose of synchronization. A wide-range, low-power delay-locked loop based (DLL-based) frequency multiplier with the PMOS active load and adaptive body biasing (ABB) circuit is proposed. Adding the PMOS active load in the delay cell has the inductive-peaking effect to increase the operation frequency range. With the clocked-power ABB current mode logic (CML) exclusive-OR (XOR) circuit, the frequency multiplier can achieve power saving to 54.9% compared with conventional CML XOR circuits. The frequency multiplier can generate N times of frequency of the input clock when the number of delay cells (N) in the Voltage Control Delay Line (VCDL) is even. The proposed DLL-based frequency multiplier can operate from 80MHz to 2.1GHz using 0.18μm CMOS process. The measured peak-to-peak jitters of the DLL core are 30.56ps at 330MHz and 70ps at 80MHz. The power consumption and jitter of the proposed frequency multiplier at 2.1GHz are 30mW and 26.7ps, respectively. The SerDes interface can also apply to video transmission. In general, when an image is transmitted by the transmitter, the transmitted video may be included noise such Gaussian noise and White noise. Therefore, an important problem of video/image processing is to effectively remove noise from a received image while keeping its features. Therefore, we propose a switching bilateral filter (SBF) with a texture and noise detector for universal noise removal. Operation was carried out in two stages: detection followed by filtering. For detection, we propose the sorted quadrant median vector (SQMV) scheme, which includes important features such as edge or texture information. This information is utilized to allocate a reference median from SQMV, which is in turn compared with a current pixel to classify it as impulse noise, Gaussian noise, or noise-free. The SBF removes both Gaussian and impulse noise without adding another weighting function. The range filter inside the bilateral filter switches between the Gaussian and impulse modes depending on the noise classification result. Simulation results show our noise detector has not only high noise detection rate but also high classification rate for both salt-and-pepper and uniform impulse noise. Unlike the majority removing both type of mixed noise, the SBF achieves high PSNR and great image quality in removing salt-and-pepper, uniform and Gaussian noise.