Abstract
To continuously improve device performance with the shrinkage of device dimension, some novel devices like the fully-depleted silicon-on-insulator (FD-SOI) and symmetric double gate (SDG) transistor have been proposed. Various HfxTaySizN metal gate electrodes were developed to achieve work function near the mid-gap and excellent thermal stability. Furthermore, Hf0.19Ta0.41Si0.26N0.14, demonstrated excellent electrical performances in hysteresis effect, interface trap density, stress-induced leakage current and excellent thermal stability as well. The characteristics of integration of high-k gate dielectric and metal gate electrode are also studied. Interaction of HfxTayN metal gate with SiO2 and HfOxNy gate dielectrics has been extensively studied. Metal-oxide-semiconductor (MOS) device formed with SiO2 gate dielectric and HfxTayN metal gate shows satisfactory thermal stability. Secondary ion mass spectroscopy (SIMS) analysis results show that the diffusion depths of Hf and Ta are less significant in SiO2 gate dielectric than that in HfOxNy. Compared to HfOxNy gate dielectric, SiO2 shows better electrical properties, such as leakage current, hysteresis, interface trap density and stress-induced flatband voltage shift. With an increase in post metallization annealing (PMA) temperature, the electrical characteristics of the MOS device with SiO2 gate dielectric remain almost unchanged, indicating its superior thermal and electrical stability. As the process technology continues to scale, the stability of SRAM is a growing concern in the cell design. Static noise margin (SNM) can serve as a figure of merit in stability evaluation of SRAM cells. A new methodology is proposed to evaluate SRAM cell stability and cell performance to optimize cell design. The sensitivity of SRAM static noise margin and write margin are also studied based on metal gate “HfTaN” with different gate dielectric layer “SiO2” and “HfOxNy” process to develop an SRAM cell stability fault model concept and evaluate SRAM performance. Application of high-k and metal gate is profitable for SRAM application. This result is helpful for usage of high-k and metal gate stacks in sub-45nm and behind.