Abstract
Metallic Schottky barrier source/drain has been intensively studied because of their potentiality to minimize parasitic source/drain resistance in CMOS technologies. The Schottky barrier devices generate particular carriers transport associated with the Schottky barrier junctions. Dopant-segregated (DS) technique was widely adopted to tailor Schottky barrier junctions, increasing on-state current and suppressing ambipolar conduction. Because Schottky barrier junctions can produce a strong enhancement of hot-carrier generation to ensure a large gate current at low voltages, the Schottky barrier source/drain is used in nonvolatile charge-trapping memory cells to exhibit unique source-side electron programming and drain-side hole erasing. This dissertation elucidates the differences of physical mechanisms between the DS-structured and non-DS Schottky barrier charge-trapping cells and discusses the coupling of Schottky barriers and trapped charges involved in cell programming and reading. Two-dimensional device simulations were employed to investigate the cell conduction, programming, and erasing. Since the DS layer tailors the effective Schottky barrier height in Schottky barrier devices, the DS condition has a key function in determining the injected mechanisms and locations of cell programming and erasing. It narrows the source-side Schottky electron barrier to minimize the source-side lateral field, thereby reducing the source-side electron programming. It also decreases the drain-side hole erasing because of the reduced hole drain current and drain-side lateral field. Based on the injected mechanisms, two categories of DS-structured cells are classified: 1) light DS Schottky barrier-like cell and 2) heavy DS conventional-like cell. The Schottky barrier-like cells exhibit enhanced programming/erasing characteristics with better short-channel effects, whereas they generate low electron drain currents for cell reading. The tradeoffs inherent in the cell programming/erasing, the short-channel effect, and the cell reading necessitate optimizing the DS profiles in scaled Schottky barrier charge-trapping cells. Based on cell scalability and low-power operation, the intrinsic Schottky barrier source/drain should be the most appropriate in NOR-type charge-trapping cells to ensure efficient programming/erasing. Using numerical iterations, this thesis precisely examines the coupling of Schottky barriers and trapped charges involved in cell programming and two-bit/cell reading. In the Schottky barrier cells, both the conduction and injection of electron carriers depend on the Schottky source barrier lowering. The local trapped charges counteract the gate-controlled field, reducing the programming efficiency, and moving the subsequent injections away from the source edge. The distribution of total trapped-charges is considerably wider than that of the initial injection. Because of source-side conduction, the excellent screening of second bit effect in the Schottky barrier cells is beneficial to operate the NOR-type multi-bit/cell charge-trapping memories.