Abstract
As the technology of the semiconductor process continues its scale miniaturization and improvement of electronic device performances, next-generation IC chips with Cu/low-k stacked structures and adopting the fabrication of a damascene module are being developed to meet the urgent requirements of reducing high RC delay so as to obtain high-speed signal communication. However, due to the mismatch in the CTE as well as a mismatch of elastic modulus existing in dissimilar materials, there is a high probability that doing so may contribute to interfacial cracks occurring or propagating within the multi-level interconnection system, composed of the copper interconnections and low-k materials, as a result of poor adhesion and intrinsically lower fracture toughness of the low-k materials when temperature loads are applied during the wafer level and the packaging level stages. Meanwhile, the phenomenon of crack growth is also observed in other devices such as the fracture of solder joints in advanced packaging structures. Therefore, this fracturing problem has become one of the critical issues for thermo-mechanical device reliability, which needs to be resolved urgently. In this research, a novel tie-release crack prediction technique based on finite element calculation is developed to investigate the stress-induced impacts on the thermo-mechanical reliability of electronic interconnects during the whole cracking growth process of the bi-material interface. In addition, the entire processes of a simulation-based optimal design combined with statistics techniques are systemically constructed to study the impacts of the significant design parameters on the concerned response by using the sensitivity analysis and sequential RSM methodologies. Thus, the mechanical reliability of the new device will not only be greatly enhanced at the initial design stage, but the technique will also reduce the amount of required tests. On the other hand, when utilizing the proposed tie-release crack prediction technique through the use of a suitable integral contour path with sufficient finite element meshes adjacent to the crack tip, the cracking energy, which determines the opportunity of crack advance, is estimated by the J-integral method to tend toward a stable value. All analytic results indicate that a rectangular integral path is suggested for obtaining a stable J-integral value. In addition, the following conditions must also be satisfied with the J-value estimation in a FEA: (a) the crack tip must be at the center of the contour path, and the long side of the abovementioned contour path must be parallel to the direction of the crack propagation, (b) the aspect ratio of the contour path coming from the short side divided by the long side should be less than 0.1, and (c) the short side of the contour path, as well as the direction of the film thickness should include at least three layers of elements in each side of the fracture surface. Moreover, by means of a 4-point bending test FEA model and a comparison with the relative experimental data of multi low-k dielectric films, the methodology of finding a stable J-integral value for dissimilar materials has been validated to be reliable. In addition to the failure criterion based on the energy method referred to above, the simulation of an interfacial fracture based on the critical interfacial stresses estimation that must be determined experimentally is also adopted to judge the occurrence of the crack. To ensure that the proposed prediction methodology is correct and feasible, both wafer-level and packaging level device structures such as a PBGA package with Cu/low-k stacked structures, as well as the DL-WLCSP, respectively, for the fracture issues are implemented as the test vehicles to demonstrate the difference from the traditional prediction techniques. All analytic results reveal a good agreement with the consequences of relative device tests. Based on the above, the development of design/prediction methodologies for the cracking/delamination issues regarding the mechanical reliability of advanced electronic devices presented in this investigation can be demonstrated and widely applied in various device structures. In other words, both the feasibility and the correctness of the novel prediction crack techniques based on fracture mechanics for resolving the problem of the interfacial crack occurring, growing and extending, in dissimilar materials are the major contributions of this research.