Abstract
Since the first integrated circuit was created in 1958, the integrated circuit technology has widely influenced our daily life. This technology has been applied to various modern electronic devices such as computers, mobile phones, audio and video devices, medical electronics and so on. The major component of the integrated circuit is the transistor and most of the transistors used today are the metal-oxide-semiconductor field-effect transistors (MOSFETs). With the progress of process technology, the dimension of transistors shrinks and therefore the number of transistors per unit area increases in the integrated circuits accordingly. At the beginning of 1960’s, Gordon Moore forecasted that the numbers of transistors per unit area will double every eighteen to twenty four months. It becomes more difficult to follow Moore’s law when the channel length of MOSFETs shrinks below 50 nm. The two major issues of further scaling are the following, first, the appropriate high-dielectric-constant thin film to replace the traditional silicon dioxide and, secondly, the mobility of carriers in the channel needs to be enhanced by strained silicon. Therefore, this thesis focuses on these two issues. The first part of the thesis describes the reliability properties of LaAlO3 gate dielectric and the second part on the modeling of nMOSFET with strained silicon. In the first part of this thesis, MOS capacitors and nMOSFETs with LAO gate dielectric were fabricated and various reliability properties, including time dependent dielectric breakdown, stress induced gate leakage current and positive bias temperature instability, were all studied. In the second part of the thesis, strained n-channel MOSFETs with various channel widths and lengths were fabricated and the stresses in the channel were simulated. The enhancement of the on-state drain current in the channel was then calculated by the simulated stress in the channel and compared to the measured data.