Abstract
As CMOS technology continuous to scale down, Integrated circuits (ICs) have been wieldy applied to various applications such as remote sensors and smart portable devices due to the benefits of smaller area, higher complexity, and high performance. On the other hand, the limited power budget makes low power design as an indispensable part. However, the existing low power design schemes may cause reliability issues and threaten the integrity of the ICs, which comes up with an open space for further investigation. In this dissertation, we address three major reliability challenges for modern low power IC designs, i.e., power gating design, 3D-ICs, and dynamic voltage/frequency scaling, and propose corresponding efficient and intelligent methods to address the problems to gracefully trade-off between design cost and reliability. First, retention registers have been widely used in power gated designs to store data during sleep mode. However, their excessive area and leakage power render it imperative to minimize the total retention storage size. The current industry practice replaces all registers with single-bit retention ones, which significantly limits the design freedom and yields sub-optimal designs. Towards this, for the first time in literature, we propose the concept and the design of multi-bit retention registers, with which only selected registers need to be replaced. The technique can significantly reduce the number of bits that need to be stored and thus the leakage power, but needs several clock cycles for mode transition. In addition, an efficient assignment algorithm is developed to minimize the total retention storage size subject to mode transition latency constraint. Experimental results show that our framework on average can reduce the leakage power in sleep mode by 84% along with additional mode transition latency of 6 to 11 clock cycles, compared with the single-bit retention register based design. Second, in three-dimensional integrated circuits (3D ICs), Through Silicon Via (TSV) is a critical enabling technique to provide vertical connections. However, it may suffer from many reliability issues such as undercut, misalignment or random open defects. Various fault-tolerance mechanisms have been proposed in literature to improve yield, at the cost of significant area overhead. In this part, we focus on the structure that uses one spare TSV for a group of original TSVs, and study the optimal assignment of spare TSVs under yield and timing constraints to minimize the total area overhead. We show that such problem can be modeled as a constrained graph decomposition problem. Two efficient heuristics are further developed to address this problem. Experimental results show that under the same yield and timing constraints, our heuristic can reduce the area overhead induced by the fault-tolerance mechanisms by up to 61%, compared with a seemingly more intuitive nearest-neighbor based heuristic. Third, Dynamic voltage scaling (DVS) has been widely used to suppress power consumption in modern designs. The decision of optimal operating voltage at runtime should consider the variations in workload, process as well as environment. As these variations are hard to predict accurately at design time, various deterministic and reinforcement learning based DVS schemes have been proposed in the literature. However, none of them can be readily applied to designs with graceful degradation, where timing errors are allowed with bounded probability to trade for further power reduction. In this part, we propose JPDF based and Q-learning based DVS scheme dedicated to the designs with graceful degradation. We compare it with deterministic DVS schemes, i.e., a stepping based scheme. Experimental results on three 45nm industrial designs show that the proposed Q-learning based scheme can achieve up to 83.9% power reduction with 0.01 timing error probability bound. To the best of the authors’ knowledge, this is the first in-depth work to explore reinforcement learning based DVS schemes for designs with graceful degradation.