Abstract
Analog to digital converter (ADC) plays an important role in the modern system on a chip (SoC) because it provides interfaces between the real world and the virtual digital systems. Recently, the demand on low power ADC has dramatically increased due to the growth of portable devices and environmental monitoring network. This dissertation presents three successive approximation register (SAR) ADCs with good power efficiency at low voltage. The first part of this dissertation presents an 11-bit two-step switching SAR ADC. It only requires 64 unit capacitors and employs supply-boost technique of comparator to operate at low supply voltage and reduce meta-stability. The prototype, fabricated in 0.18 μm CMOS technology, consumes 5.02 μW at 500 kS/s from a 0.6 V supply and achieves an ENOB of 9.45 bits and a Walden's figure of merit (FoMW) of 14.34 fJ/conversion-step, respectively. The second part presents a 10-bit merge-and-split (MS) SAR ADC, which reduces DAC switching energy by 83% compared with conventional one. To operate at low voltage with good linearity, a new double-bootstrapped sample and hold (S/H) circuit is proposed. The test chip fabricated in 90 nm CMOS. With a 0.3 V supply and a Nyquist input, it consumes 35 nW at 90 kS/s and achieves an ENOB of 8.38 bits and a FoMW of 1.17 fJ/ conversion-step. The third part presents a 10-bit first 2-bit guess (F2G) SAR ADC, which reduces DAC switching energy by 90% and improves the DNL and INL by √3/2 compared with conventional one. By the proposed comparator with stacked input pair and majority-vote comparison at the conversions of LSBs, the comparator power is reduced. Implemented in 90 nm CMOS technology, the prototype consumes 67.3 nW at 150 kS/s from a 0.3 V supply and achieves an ENOB of 8.85 bits and an SFDR of 70.7 dB at Nyquist input, respectively. The resultant FoMW are 0.97 fJ/ conversion-step.