Abstract
Memories, the basic components of digital systems, are becoming the dominant factor of the area and manufacturing yield of a system chip. The size and density of semiconductor memories is rapidly growing, making them increasingly hard to test. New fault models and test algorithms have been continuously proposed to cover defects and failures of modern memory chips and cores. However, software tool support for automating the memory test development procedure is still insufficient. For this purpose, we developed a software framework to accelerate test algorithm evaluation, test algorithm generation, and diagnosis procedure for memories. MTIF, the Memory Testing Innovation Framework, consists of several components that can be made as stand-alone tools. Key components are the fault simulator (called RAMSES), the test algorithm generator (called TAGS), the error analyzer (called ERA), and the error-map generator (called EMAP). Efficient test algorithms can be generated automatically for bit-oriented memories, word-oriented memories, and multi-port memories, to cover 100\% faults in given set of fault models. More over, the Memory Error Catch and Analysis (MECA) system can be constructed by integrating MTIF components and the testing equipment. The MECA system provides an automatic approach to diagnose memories for design verification and yield improvement.