Abstract
This study proposed new circuit design techniques to achieve high-performance CMOS integrated amplifiers for wireless/line communications at microwave frequencies. The design concepts were demonstrated by one narrowband and one broadband amplifiers, which were both realized in the standard 0.18-μm RF CMOS technology. The measured results presented superior performances compared with other published works using a similar or even more advanced CMOS technology. The designed narrowband amplifier is a 24-GHz balanced amplifier (BA) with a gain up to 45 dB. An effective technique, π–type parallel resonance (PPR), was proposed to boost the high frequency gain of a MOSFET by resonating out the inherent capacitances. The miniaturized lumped-element coupler in the circuit occupies a chip area of only ~ 2 % compared to that of the conventional transmission-line coupler. The BA consumes 123 mW from a supply voltage of 1 V. The proposed CMOS BA presents the highest gain of 45.0 dB with a chip area of 0.97 × 0.63 mm2 (core area: 0.78 × 0.43 mm2) among the published narrowband amplifiers with similar technologies and operation frequencies. The designed broadband amplifier is a 40-Gb/s transimpedance amplifier (TIA). From the measured S-parameters, a transimpedance gain of 51 dBΩ and a 3-dB bandwidth up to 30.5 GHz were observed. A gain-bandwidth product (GBW) enhancement technique, π-type inductor peaking (PIP), is proposed to achieve a bandwidth enhancement ratio (BWER) of 3.31. In addition, the PIP topology used at the input stage decreases the noise current as the operation frequency increases. Under a 1.8 V supply voltage, the TIA consumes 60.1 mW with a chip area of 1.17 × 0.46 mm2. The proposed CMOS TIA presents a GBW per DC power figure-of-merit (GBP/Pdc) of 180.1 GHzΩ/mW.