Abstract
For the traditional SOC (System On a Chip) approach, there are many integration tasks to combine CMOS with other functional parts, and it is hard to decrease the cost with such complex processes. The SIP (System In a Package) approach, on the other hand, provides a lower cost solution, but due to the bonding wire loading, signals will suffer from serious delays In addition, bandwidth for data communication is severely limited by the number of bonding pads. Thus, we propose a modular SOC concept here to decrease the complexity of process but keep the same performance. In modular SOC, all functional modules are fabricated after completing the interconnect. This approach modularizes all the functional parts; the CMOS technology can be easily upgraded and thus eliminates the complex integration work for combing CMOS technology and functional parts. The key for the success of this advanced SOC is that the processing temperature for all functional modules must be lower than 450 degree C to allow the fabrication of modules after the interconnection. Base on this SOC concept, we proposal the COI (Capacitor-Over-Interconnect) FeRAM. For this approach, the FeRAM is modular fabricated on the top of the interconnect, so that complex integration work for combining the CMOS logic circuit and FeRAM is eliminated and the ferroelectric capacitor is not damaged by COMS interconnect process. A ZSTT (Zero Switching Transient Time) model is selection for this COI FeRAM HSPICE modeling application, because it is fully compatible with HSPICE simulator and it neglects the complex transient behavior of ferroelectric thin film. For model parameter extraction, a “ferroelectric capacitor connects with a linear capacitor” measurement set up and a pulsing rectangular input signal are chosen to provided the V-t matrix of ferroelectric capacitor, because it reveals the real FeRAM array architecture and neglect the relaxation effect for over estimating polarization. The simulation results are verified by comparing with real measurement data and those data are quite match. A special 1T1C/2T2C compatible memory array is proposed in the COI FeRAM chip design. A standard static NAND type decoder and a latch type sense amplifiers are used in this design to get robust peripheral control and sensing circuits. A novel plate line driven while bit line driven operation scheme is used in this design to archive higher chip speed. Base on the HSPICE simulation data and real chip test data, this chip design shows good electrical results and meets the original design objectives. In order to realize the COI FeRAM concept, a low temperature processed LNO/PZT/LNO ferroelectric capacitor has been demonstrated. For the first time, crystallization temperature of 350 ~ 400 degree C for PZT has been achieved. The LNO is an ideal electrode - it has low resistance, serves as an excellent seed layer, and it improves the cycling endurance. 2Pr value of 20 μC/cm2 is achieved for the low temperature capacitor, and is adequate for FeRAM application. In addition, we find that the epitaxial LNO/PZT/LNO structure improves the capacitor cycle endurance tremendously. After 1011 cycles more than 70% of Pr remains for the LNO/PZT/LNO structure. The COI FeRAM array architecture provides higher array density, since no via stacks over the capacitor. Our COI FeRAM cell provides adequate sensing margin even with a long bit line with capacitance of 800 fF. A 64Kb(2T2C)-128Kb(1T/1C) dual-mode COI FeRAM tester is demonstrated successfully by using a single polysilicon double metal 0.5um CMOS logic process plus COI process. The access time of this COI FeRAM tester is about 80ns~120ns within the Vcc range of 4~6V.