Abstract
As feature size of MOS technology continues to shrink into nano-scale, power density becomes a critical issue for transistor scaling. When power density reaches hundreds of watt per centimeter square, power noise challenges 2D chips or even 3D chips to design a reliable IC. To meet the demand of power noise reduction, three new key architectures are proposed: (1) reconfigurable Engineering Change Order (ECO) cells used as decoupling capacitors to reduce voltage (IR) drop and as functional spare cells to solve timing closure; (2) relative temperature sensor to measure accurate temperature data in hot spots to help dynamic thermal management in chip design; (3) a new architecture for power network in three dimensional (3D) integrated circuit (IC) to solve static and dynamic voltage drop in through-silicon via (TSV) technology of 3D IC. Compared with traditional ECO flow, our proposed reconfigurable ECO cell and its corresponding flow shows 15% reduction in maximum IR drop and 9% reduction in leakage before applying ECO, and 7% reduction in maximum IR drop after applying ECO, with 10% area of spare cells. In addition, it shows that there are less unsolved timing-violation paths left after applying our proposed reconfigurable ECO timing optimization flow due to less IR drop and free selection of ECO gate type. As to relative temperature sensor, compared with the absolute temperature sensor where maximum temperature error could be as high as 15℃, our relative temperature sensor shows 6.5℃ maximum temperature error with 69% area reduction using 1 um wide metal connection when 5 HBJTs (bipolar junction transistors placed at hot spots) are used in a cluster, and 5.4℃ maximum temperature error with 3% area overhead using 10 um wide metal connection when 8 HBJTs are used in a cluster, in the best case. Both in single-power-domain and multiple-power-domain of the power network in 3D IC, our proposed STDN architecture demonstrates good performance in 3D floorplan, IR drop, power noise, temperature, area and even the total length of signal connections for selected MCNC benchmarks.