Abstract
As the technology node scales down to nanometer range, packages and chips both face many challenges in physical design and manufacturing process. With the increasing complexity of circuit design in recent years, package pin assignment and printed circuit board (PCB) escape routing have become extremely difficult due to the fast increasing pin count of a package. However, most previous works often treat the pin assignment and the escape routing as two independent problems without a global view of co-design. Besides packages, a new challenge arises in the manufacturing process of a chip. Single-exposure immersion lithography has difficulty in printing the layout pattern under 22nm technology node and beyond. Double patterning lithography (DPL) has emerged as a promising solution to print layout pattern for sub-22nm technology nodes. It is desired to consider DPL during the detailed routing stage so that the layout can be decomposed effortlessly with the minimum number of stitches. In this dissertation, we propose three optimization techniques to solve the physical design problems including the PCB escape routing and chip-level double patterning-aware detailed routing. First, we propose a simultaneous approach that can solve the constrained pin assignment and escape routing for an FPGA package on a through-via-based PCB. Second, we address the pin assignment and escape routing for a package on a blind-via-based PCB. We propose a pin assignment and blind-via usage co-optimization algorithm and a simultaneous multi-layer escape routing algorithm based on the blind-via technology. Finally, we propose a double patterning-aware detailed routing algorithm to balance the mask usage. Extensive experimental results show that our proposed optimization techniques are effective and efficient for PCB escape routing and double patterning-aware chip routing.