Abstract
To satisfy low-power and high-performance requirements, modern designs support advanced features such as multi-power modes and out-of-order transactions. However, these features may lead to occurrences of timing errors, soft errors, and deadlocks. To efficiently tolerate or avoid the occurrences of these errors and deadlocks, we propose several gate-level and architecture-level optimization methods. First, we propose a gate-level timing optimization for multi-power mode designs. We use Adjustable Delay Buffers (ADBs) to construct a tunable clock tree so that useful skew can be assigned for different power modes. Then, we assign the delays of the ADBs for each power mode by Linear Programming (LP). A speedup theorem is proposed to greatly reduce the inequalities for the LP. We also propose an efficient heuristic to select the positions of ADBs. Second, we present a dual-level soft-error tolerant design methodology to trade off performance, power, and reliability for different applications. Four novel detection and correction Flip-Flop (FF) structures are proposed to provide different levels of tolerance capability against soft errors. Then, architecture-level vulnerability analysis and gate-level susceptibility analysis are employed to identify weak FFs that can easily cause program execution errors. An optimization framework is developed to synthesize the proposed four novel FF structures into weak and highly-observable storage bits. Third, we develop architecture-level deadlock-free mechanisms for the designs supporting out-of-order transactions. We provide a novel ID assignment mechanism which guarantees the issued transactions to be deadlock-free. Flexible rules are also presented for the ID assignment problem to greatly reduce the number of transaction stalls.