Abstract
Technology advancements in the last four decades is enormous. This is enabled by cheaper, more complex and functionality richer "smart devices". Research innovation, invention and growth in integrated circuit fabrication and application has lead this generation technological growth. Artificial Intelligence, Quantum computers and Internet of Things promise to take industrial revolution forward and semiconductor devices will be the backbone of these three key electronics novel research fields. CMOS scaling and Moore's law are the driving force of semiconductor industries around the globe. The CMOS scaling delivers (1) high performance, (2) low power and (3) low cost per transistor for integrated circuit (IC). But as we keep scaling down aggressively, Si transistors which ruled the semiconductor industry may not sustain the scaling anymore. To compensate the challenges, CMOS device channel materials and many new device architectures and new device geometries are being explored by researchers, material scientists. Process innovation and reliability of the new materials were also extensively researched. As we move on from conventional silicon devices to the future of quantum devices, traditional laws of semiconductor devices are not anymore enough to predict the device characteristics. At quantum atomic scales, sub 10-nm CMOS v devices, quantum confinement effects cannot be ignored. Detailed modeling and simulation study on quantum effects that arise due to the scaling becomes a must before actual fabrication of devices. many different simulation tools based on Density functional theory (DFT), local-density approximation (LDA), generalized gradient approximations (GGA), meta-GGA, drift diffusion, density gradient models with quantum correction, non-equilibrium green function formalism, multi-band Monte Carlo simulations were carried out to predict device characteristics as accurately as possible. Device reliability and aging in nano-scale MOSFETs is one of the main challenges within the semiconductor industry. Some of the challenges that must be alleviated when feature size is being scaled down, are random discrete Dopant RDD, RDD fluctuation RDDF, polysilicon gate granularity PSG, metal grain granularity MGG, random telegraphic noise RTN, bias temperature instabilities BTI, trap assisted tunneling TAT, interface trapped charges ITC, thermal budgets, short channel effect (SCE) etc.. New concepts like "Junctionless" transistor operation mode where homogenous doping is used has a promising future in sub 10nm device technology nodes. the concept of the bulk and junctionless (JL) field-effect-transistor (FET), which contains a heavily, uniformly, and homogeneously doping species in the channel and source/drain (S/D), has been proposed and researched extensively now. Such a JLFET device is also demonstrated with poly-Si thin film transistor (TFT), which is suitable for monolithic three dimensional (3D) vertically stacked integrated circuits (ICs) and to continue the applicability of Moore’s law. Moreover, compared with JL SOI FinFETs, JL bulk FinFETs show better short channel characteristics and threshold voltage (Vth) control by tuning substrate doping concentration. However, JL bulk FinFETs have difficulties in fabrication of the junction-isolated JL device, which needs to be free from leakage-induced substrate current. In addition, JL channel must be small enough to achieve outstanding turn-off characteristics. The small-dimensional channel makes process control difficult and possibly leads to an increase vi of the series resistance in the S/D accompanying a decrease of drain current in bulk and SOI JL FETs. We explore options for device scaling beyond the conventional scaling path. This thesis is divided into five parts to investigate (1) Silicon Fin Field effect transistors (FinFET) at the scaling limit, (2) Germanium Fin Field effect transistors (FinFET) at the scaling limit, (3) Silicon nanowire (NW) Gate all around (GAA) transistors with atomically thin channel (4) studying Germanium nanowire (NW) Gate all around (GAA) transistors with different crystallographic orientations. (5) Vertically Stacked nanosheet gate-all-around transistors with Silicon to enable scaling beyond FinFET. In the first part, we study silicon FinFET at scaling limit. We examine the performance of the optimized 3-nm FinFET with homogeneous source and drain doping concentration in all three modes (IM, AC & JL) of operation. The transfer and output characteristics of Inversion mode, Accumulation mode and Junctionless mode devices are discussed in detail. In addition, for each case, we interpret the 3-D electron density mesh plots. The main purpose of this paper is to provide a logical understanding of the transport properties through the simulated results as the device dimension approaches gate length (LG) of 3nm. In the second part, we study Germanium FinFET at scaling limit. In this work, we analyzed the performance of scaled Germanium FinFETs and compared their device characteristics with a 3-nm bulk Silicon FinFET with similar device dimensions [13]. As Germanium is a potential material, this paper tries to explore the transport properties and the effect of quantum confinement on performance of Ge-based transistors. In this work, we for the first time report the charge distribution in different sub-bands of Ge devices. We have compared Si and Ge device density of states and band structure too. Junctionless (JL) devices with homogenous source drain doping will be the preferred mode of operation in ultra-scaled logic devices due to the various advantages such as reduced scattering and vii simpler device fabrication processes . Thus we comprehensively analyzed the JL mode of operation which will serve as a benchmark for future scaled device dimensions. In the third part, we study the Silicon gate-all-around GAA transistor with atomically thin channel. A novel, high performance low-power consumption Silicon junctionless (JL) trench gate-all-around (GAA) nanowire (NWFET) transistor with atomically-thin channel for future sub-10nm technology node is demonstrated experimentally. The major problems of scaling such as, short channel effects (SCE), threshold voltage (VTH) variation, power consumption can be attenuated by using the proposed device model. The reported device with the thinnest channel shows a sub-threshold swing (SS) of 43mV/decade which has been the record to date in trench JL GAA NWFETs. Owing to the atomically-thin channel, this device has extremely high ION/IOFF current ratio of >108. Higher BTBT generation rate when channel is scaled down to <1nm leading to quantum tunneling paves a way to achieve SS value much lower than its fundamental limit. This phenomenon is confirmed with drift-diffusion (DD), density-gradient (DG) modeled 3D quantum transport TCAD device simulation. In the fourth part, we studied the Germanium gate-all-around transistor with different crystallographic orientations. We employ a robust physics-based model solving 3D Poisson – 2D Schrödinger equation to investigate charge transport in germanium nanowire gate-all-around transistors with 3-nm gate length. We studied the effects of band structure on quantum-confined germanium and silicon nanowires. The corresponding density-of-states results were also analyzed. Different nanowire orientations have different band structure and density-of-states (DOS) due to the strong quantum-confinement effects which influence the charge carrier velocities directly. Hence, in strongly quantized germanium nanowires, change in effective masses is also significant. Analyzing the charge distribution in the different valleys and sub-bands show that multiple valley degeneracy gives high density-of-states for Ge nanowire in <110> orientation compared to <100> <111> orientations; hence, <110> viii oriented Ge nanowire is expected to deliver improved performance at ultra-scaled dimensions. Finally, we modeled and simulated a stacked nanosheet gate all around GAA Silicon transistor that can enable current FinFET scaling and that had been successfully demonstrated by semiconductor leader IBM. We also analyzed the device operation in inversion and accumulation mode. Apart from the device characteristics, the circuit characteristics need to be analyzed in detailed manner. we investigated inverter operation and timing characteristics of stacked nanosheet gate all around GAA Silicon transistor operating in Junctionless mode.