Abstract
New generations of display technologies provide a significantly improved dynamic range compared to conventional display devices. Inverse tone mapping methods have been proposed to convert low dynamic range (LDR) images to high dynamic range (HDR) ones, and several of them require multiple-exposures LDR images of the same scene as inputs. However, the vast majority of LDR images and videos available have only one single exposure. In this dissertation, we propose a region-based enhancement of the pseudo exposures to generate an HDR image. First, we present an exposure dependent $S$ curve to convert one LDR image to the pseudo-multiple-exposures images. Only certain regions of the pseudo-multiple-exposures images contain noticeable detailed information. We propose a region-based enhancement on the pseudo-multiple-exposures images to boost details in the most distinct region. Thereby the region-enhanced pseudo-multiple-exposures images are fused into an HDR image. The fused image thus enhances details in the brightest region of the darkest image and the darkest region of the brightest image. Compared with other inverse tone mapped methods, our method generates the lower total contrast error which is measured under the dynamic range independent image quality assessment method. In this dissertation, we analyze the performance of implementing inverse tone mapping operation in various multi-core environments. We parallelize the two procedures to produce five HDR images and different weighting values. The ratio of the instruction counts for producing five HDR images and weighting values are both reduced, and the total simulation time decreases around 70% under six-core environment. The reduction is because these functions are implemented parallel with multi-thread on a multi-core platform. The analysis of hardware performance shows that our proposed method is easy to be realized in a multi-core system to speed up the performance. The technology to display HDR images or videos on conventional LCD devices is called tone mapping which has the different algorithms that have been developed in the past decade. An ideal HDR tone mapping processor should have some characteristics such as a robust core functionality, high flexibility, and low power consumption. Therefore, an $ARM^{TM}$-core-based System-on-Chip (SoC) platform with an HDR tone mapping application-specific integrated circuit (ASIC) is suitable for such applications. In this dissertation, we present a systematic methodology for the development of a tone mapping processor of optimized architecture using an ARM SoC platform, and illustrate the use of this novel HDR tone mapping processor for both photographic and gradient compression. Optimization is achieved through four major steps: common module extraction, computation of power enhancement, hardware/software partition, and cost function analysis. Based on our proposed scheme, we present an integrated photographic and gradient tone-mapping processor that can be configured for various applications. This newly-developed processor can process the image size 1024X768 at 60 frame per second, runs at 100 MHz and consumes a core area of 8.1 mm^2 under TSMC 0.13 um technology, resulting in a 50% improvement in speed and area as compared with previously described processors.