Abstract
Climate change by carbon dioxide emission has emerged as a big issue of the world. The electrical power energy saving and optimization are necessary as a whole to be solved for a sustainable world. Recently high voltage integrated circuits (HVICs) have been receiving interest and becoming key technologies to improve power conversion and controls from the process of energy exchange and minimize energy loss for use in the various high-voltage (HV) applications, including switch-mode power supplies, LED lighting, electronic ballast, motor drivers. Lateral high voltage semiconductor power devices have been widely used in HVICs design to achieve low power consumption and high energy transfer efficiency. In recent years, there have been lots of efforts and new innovative device structures proposed to minimize the on-state resistance and conduction power losses while maintain the high blocking voltage of power devices. The design concept most commonly applied in modern high performance power devices is the RESURF (REduce SURface Field) technique. In this thesis, important parameters of the p-buried layer of a high voltage RESURF PN diode are comprehensively analyzed and discussed in terms of effects on device performance, including breakdown voltage and specific turn-on resistance, Ron,sp. The key parameters are identified and guidelines for designing the vertical position, lateral location, and doping concentration of the p-buried layer are suggested to optimize the device turn-on resistance and breakdown voltage tradeoff. The experimental results demonstrate that the PN diode with the proposed p-buried layer optimization design can improve breakdown voltage by 30.7% but with very little (2.7%) sacrifice in the specific on-resistance Ron,sp. The physics mechanisms and device design guidelines discussed in this paper was further extended to the design of high voltage LDMOSFET (Laterally Diffused Metal-Oxide Semiconductor Field-Effect Transistor). Two-dimensional simulations displayed that, compared to conventional triple RESURF structure, the present device provides a 4-fold reduction in the surface electric field on the source side and a 32% improvement in blocking voltage. Experimental results demonstrate that the BV-Ron,sp figure of merit (FOM) approaches the ideal Baliga’s power law. The specific on-resistance shows superior 40% lower performance than published JI (Junction Isolation) LDMOSFET device families. The optimal charge balance and geometrical design to achieve the lowest specific on-resistance (Ron,sp) with the desired maximum high breakdown voltage are displayed and discussed by simulations and experiment results. This thesis extends the investigation into device SOA (Safe Operating Area) in terms of p-buried RESURF designs. The device SOA (safe operation area) is crucial to the performance and robustness of circuit designs for switching power supply applications. When the drain bias (VDS) of the device approaches the avalanche breakdown voltage, a parasitic n-p-n bipolar turn-on at source side is usually occurred, which causes early on-state breakdown in the LDMOSFET and limits the SOA range. The LDMOSFET with the proposed p-buried layer optimization design shows effectively suppressing the parasitic n-p-n bipolar on-state breakdown and enhance increasing the SOA capability. By triggering a Kirk effect to start before parasitic bipolar turn-on in the LDMOSFET, the on-state drain current (IDS) breaks the traditional Quasi-saturation limit and is dramatically expanded to be almost proportional to VGS at high drain bias (VDS) area, which substantially increases both current handling capability and the SOA margin when the power device is transiently operating between on-state and off-state. The experimental result shows that the SOA of the present device is remarkably increased by over 2-fold, which much benefits the performances of circuit designs for switching power supply applications.