Abstract
Three-dimensional integrated circuit (3D IC) is considered one of the most promising approaches at the limit of device scaling. The advantages of shorter interconnect lengths, smaller form factor, higher packing density, and the flexibility of heterogeneous integration, are realized by using through-silicon vias (TSVs) to connect the vertically stacking dies. However, the reliability issues, such as higher temperature effects and lower TSV yield rates, have become one of the major obstacles for 3D IC mass production. Furthermore, it is very arduous challenge to implement a single design to satisfy complicated clock tree constraints for an energy-efficient design with numerous operation power modes. To address the aforementioned issues, we originate three innovative ideas in this dissertation. First, for the issue of low TSV yield rate, a brand-new TSV fault-tolerant unit (TFU) is set forth to achieve yield improvement for the clock network of 3D ICs. The main idea is making use of a part of existing resources to lower the cost induced by establishing the fault-tolerant mechanisms. In the second work, we introduce a creative method, which significantly accelerate the speed of thermal simulation. By utilizing the method, we realize a real time thermal-aware task allocation, which can maintain the high accuracy property as well. Last, a power-mode-aware (PMA) clock skew optimization is presented for the energy-efficient designs. Instead of using complex and expensive methodologies, we merely using devices from the standard library to resolve the challenge of skew optimization in the energy-saving design. Thus, by utilizing the three innovative ideas, the robustness of 3D ICs can greatly improve.