Abstract
Supply-voltage (VDD) scaling techniques are often employed in low power Sys-tem-on-Chip (SoC) design; however, adverse impacts such as voltage-dependent timing skews and small sensing headroom have become increasingly significant on memory circuits. In this dissertation, functional failures induced by voltage-dependent timing skews and small sensing headroom in memory circuits are investigated. Techniques to overcome voltage-dependent timing skews and reduce sensing headroom requirement are proposed. Voltage-dependent timing skews in precharge and sensing activities cause func-tional failure and reduce the speed performance of embedded memory. Data-dependent bitline leakage current further increases the timing skews and reduces the yield of memory circuit. A dual-mode self-timed (DMST) technique is developed to eliminate the timing-skew-induced failures and speed degradation across various process, voltage and temperature (PVT) conditions. Comparing to the conventional sense-tracking-only replica column schemes, DMST technique achieves high scalability and timing skews reduction for various bitline (BL) lengths. Experimental results demonstrated that the DMST technique can operate continuously over a wide range of supply-voltage, from 39.4% to 151.5% of the nominal supply-voltage VDD = 3.3V. Low supply-voltage has emerged as an effective way to reduce circuit power con-sumption. However, this approach incurs small sensing headroom which leads to speed performance degradation and read functional failure in memory circuits, particularly for those density-prioritized memories such as NAND-ROM using a longer single-ended BL sensing scheme to achieve high cell array efficiency. A data-aware sensing reference (DASR) scheme is proposed for maintaining sensing margins for both read-0 and read-1 under given timing constraints at low supply-voltage. The key mechanism involved in maintaining the read sensing margins is the adaptive changing of the reference voltage, such that the sensing headroom or potential range for read-1 and read-0 overlap, as in differential BL sensing. The fabricated 256 Kb DASR NAND-ROM macros in 90-nm bulk CMOS logic process are functional down to 0.25 V. DASR also increases the ac-cess speed by 66.7% at VDD = 0.31 V, compared with other conventional approach without the proposed DASR scheme. In summary, the DMST and DASR techniques are proposed in this dissertation to deal with the challenging design obstacles in memory circuits for reliable low power SoC implementations.