Abstract
Silicon nanowire has attracted a growing interest from semiconductor industry to replace the bulk Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory in future cell scaling, system-on-chip, system-on-panel, and 3D integration applications. However, a relatively high gate voltage is still required for the conventional nanowire SONOS cell during programming or erasing. Aggressive scaling of operation voltage is much preferred to improve cell speed, energy dissipation, periphery circuitry, and cell reliability for the use in practical embedded or mobile applications. This dissertation presents an innovative Schottky barrier Silicon nanowire charge-trapping SONOS Flash memory cell, and performs a thorough study of its operations for use in future nonvolatile memory cell. Real silicon cell fabrications and in-depth measurements are performed to examine the programming, erasing and reading operations of this new memory cell incorporated with thermal retention and cycling reliability characterizations. By applying Schottky barrier source/drain to enhance electrical field in silicon gate-all-around nanowire, the nonvolatile Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory can operate at a gate voltage of 5 to 7V for programming, and -7 to -9V for erasing through Fowler-Nordheim tunneling. The larger gate voltage is, the faster programming/erasing speed and wider threshold-voltage shift are attained. Importantly, the Schottky barrier nanowire SONOS cells exhibit superior 100K cycling endurance and high-temperature retention without any damages from metallic silicidation process or field-enhanced tunneling. In addition, a localized programing and erasing scheme can be utilized to enhance the threshold voltage shift window in this Schottky barrier nanowire SONOS cell. The breakthrough in low-voltage programming and erasing operations with simple silicidation process make the Schottky barrier silicon nanowire SONOS cell very promising in future 3D integration, system-on-chip, and system-on-panel applications.