Abstract
Due to the high demand in embedded nonvolatile memory (NVM) for integrated system on a chip (SOC), complementary metal oxide semiconductor (CMOS) process based electrically erasable programmable read only memory (EEPROM) or flash memory cells are now being widely studied. This work presents an EEPROM and a flash memory cells fabricated by standard CMOS logic process along with compact cell sizes. A new EEPROM cell, which consists of two N-channel metal-oxide- semiconductor field effect transistors (N-MOSFET) in series, is programmed by select-gate-controlled drain avalanche hot hole and is erased by channel hot electron injection. The cell can be programmed and erased within 5 ms along with endurance up to 105 cycles, and 1000 hours of data retention at 150˚C. Without a P-well or an N-well serving as a coupling gate, the novel cell provides the smallest area size per bit that has been reported for the logic-process-based single-poly EEPROM memory. In addition, with a new array architecture, an N-MOSFET flash device, which requires the smallest bit area among the reported CMOS-logic-process-based flash memory cells, is successfully demonstrated. Reliability characteristics in this array are thoroughly investigated in order to set the proper operation conditions. A self-convergent programming scheme for the novel EEPROM memory cell is proposed for multilevel or analog storage. In addition, a compact SPICE sub-circuit model of the cells has been established to facilitate the circuit simulation while the cells interface with the peripheral circuits. This is critical to the development of analog nonvolatile memory applications. With its small cell size, full compatibility with standard CMOS logic process, low operation voltage, complete SPICE sub-circuit model as well as self-convergent multilevel/analog data storage, the novel EEPROM/flash memory cells can be easily adapted to various embedded applications.