Abstract
Due to the fast development of internet applications and handheld electronic products, demands of various memory modules in ultra-large scale integration (ULSI) circuits increase every year. For non-volatile data storage applications, emerging memories such as phase change random access memory (PCRAM), magetoresistive random access memory (MRAM) and resistive random access memory (RRAM) were investigated. These next-generation nonvolatile memories (NVM) have the advantages of high storage density, excellent reliability and high write/read speed. In this dissertation, a new high-density via RRAM which is fully compatible with aluminum-based complimentary metal-oxide-silicon (CMOS) logic back-end-of-line (BEOL) process are proposed and studied first. This device can be easily implemented through special design in the single mask layer layout. This device exhibits excellent electrical characteristics and has the feature to achieve ultra-high storage density array in a repeatable pattern in standard BEOL layers. As CMOS technologies push forward, the fabrication method of via in BEOL evolves from the traditional single-damascene method to dual-damascene method and the material of via also change from aluminum to copper. In addition, a back-end selector, which compatible with this copper-based via RRAM, is developed to be stacked above the via RRAM to achieve 1D1R cross-point memory array, making 3D-stackable memory array possible. Finally, a novel twin-bit via RRAM is also demonstrated in this dissertation. The novel memory cell not only can be fabricated in advanced copper-based technology, but also enable the capacity of two bits storage and self-rectifying characteristic. These different via RRAMs all possess advantages such as small cell size, CMOS compatibility, 3D stacking ability, high switching speed, good reliability. Therefore, via RRAM is expected to become available solution for next-generation high-density NVM.