Abstract
In this work, we comprehensively study the device fabrication, electrical characteristic, and reliability of the various novel nano-scale Junctionless fin field-effect transistors for three-dimensional (3D) stacked IC application. In the first part of this work, the LTPS JL-GAA TFTs with ultra-thin channel are successfully fabricated by oxidation thinning method. Our JL device shows quasi-crystal channel due to the reduction of grain boundaries and defects, beneficial for excellent electrical performance. This process is simple and compatible with existing CMOS processes. Such a GAA JL feature simplifies the S/D engineering and the DIBL is very small. The low Ioff and steep SS in JL-GAA TFTs result in high on/off current ratio up to 108, which can be used in high-speed and low power consumption applications. We also measure the breakdown voltage of such device and compare it to IM TFT. Our JL TFT obtains higher breakdown voltage because the electric field in the device is uniformly distributed liked a resistor, indicating the potential of high-voltage application. The junctionless transistor is proposed to be a future device because of the simple fabrication and suffered the suppression of On-current owing to the thin channel structure. In the second part of this work, the raised source and drain (RSD) structure is combined with the juncitonless transistor for the improvement of On-current. In the basic electrical measurement, the On-current of the RSD device almost reaches 1A that is ten times for that of the non-RSD devices. The RSD juncitonless device gets the steep sub-threshold swing (SS=100mV/dec.) and the Off-current is low (10-14A) due to the remained thin channel structure. For reliability experiment, the temperature and the stress tests are taken for the RSD junctionless device. When the RSD junctionless device is heated up, the positive shifting of threshold voltage, degradation of SS and increase of the On-current as well as Off-current could be observed. The stress operation makes the electrical characteristics of the RSD junctionless device changes due to the trapped carriers injected by gate at the edges of the gate insulator. The special structure of the N-type RSD junctionless device called the dual gate is discussed. The two gates at the same layer would make the threshold voltage become tunable flexibly. For the N-type RSD junctionless device, when the bias-gate voltage is negative, the Vth would shift toward the right side. When the bias gate voltage is positive, the Vth would shift toward the left side. It should be noticed that the shifts of Vth is linear regression with the bias gate voltage as well as the change of the On-current fits the quadratic regression. In the last part of this work, the new structure of the junctionless device is brought up called Hybrid P/N channel. The idea of the Hybrid P/N channel is intrigued by the bulk device. The different type layers are stacked as the channel to enhance the simplicity of the fabrication for the thin channel. The performance of the Hybrid P/N is good with the low SS (64mV/dec.). The simulation is added for proving the existence of the depletion region. Using different doping concentration in Hybrid P/N channel devices can adjust Vth. In further, using back-gate achieves device multi-Vth adjustment without adding process budget and device performance optimization for increased Ion simultaneously decreased Ioff via negative back-gate bias, which becomes the key technology in low-power circuit and power management applications. We also success demonstrates a 3D stacked hybrid P/N layer in 3D stacked integrated circuit (IC) applications to increase transistor density for continuing Moore’s law, which provide valuable information regarding their practical industrial and academic applications. The 3D stacked hybrid P/N layer can increase on-state current and maintain low leakage current, small SS and great DIBL characteristics of short channel effect.