Abstract
The objective of this dissertation is to investigate the feasibility of continued scaling for nanoscale floating gate NAND flash memory by means of integration optimization and novel process application. The analysis of anomalous tunnel oxide re-growth has been clarified and has obtained good reliability from shallow trench isolation modification. The functionality of interpoly dielectric layer constrained by coupling ratio reduction is enhanced using plasma nitridation method; simultaneously, aluminum oxide is evaluated as candidate for future interpoly dielectric material. The size effect of word line is mitigated by using process flow design, and then the low sheet resistance is proposed for achieving fast programming speed. The bit line contact with high aspect ratio structure suffered from severe junction leakage owing to silicon substrate loss; a novel selective epitaxial silicon growth technology is proposed as salicide sacrifice layer for junction leakage current reduction. To incorporate our process modification with novel technologies, the floating gate NAND can be easily extend to sub- 50 nm generation. First of all, the advanced high-density plasma (HDP) method for self-aligned shallow trench isolation (SA-STI) suffers from existed moisture during trench gap filling, and then induces abnormal tunneling oxide re-growth; consequently, it probably exhibits poor tunnel oxide qualities. The optimal STI integrated process is proposed to mitigate moisture encroachment of tunnel oxide. Secondly, for nano-scaling dimension of memory cell, coupling capability between control gate and floating gate is gradually degraded, thus program / erase speed both face critical challenge; plasma nitridation of interpoly dielectric are proposed to enhance gate’s coupling and program / erase speed. Besides, solutions of retention problem by oxidation process of bottom oxide are provided. To evaluate higher dielectric constant material as future IPD candidate, SiO2-Al2O3-SiO2 (OAO) stacked film instead of conventional IPD material is studied for thermal resistance, lower current leakage and less electron trap. Thirdly, sheet resistance (Rs) reduction of WSix gate as well as integrated gate process optimization is explored in detail for WSix extrusion investigation and operation speed improvement. Consequently, the selective epitaxial growth silicon (SEG) technique is evaluated to reduce junction leakage for bit line contact without sacrificing contact resistance. To adopt our studying results, the conventional floating fate NAND flash structure is capable of extending to 50 nm node and beyond.