Abstract
Since the first semiconductor integrated circuit (IC) was invented, the function and efficiency of IC was rapidly boosted as the advance of the geometric scaling technique. Through the advancement of the semiconductor technology, the transistor density in the IC becomes higher and the performance of the electrical device becomes more powerful by integrating multi-functions in one single device. However, as the size of the transistor comes to the nanoscale region, the geometrical scaling technique will face the physical limitations and the development on the advanced semiconductor device as well as the subsequent package process of the devices confront unparalleled challenge. The strained silicon technique which introduces the mechanical stress into the channel of the transistor can improve the carrier mobility in the device and has emerged as the next scaling vector. Besides, to develop new materials, the low resistance metal conduction material and low dielectric constant material (e.g. copper/low-k material), are needed for the multilevel interconnection to overcome the time of RC delay which rises to the level and can not be disregard when the density of the transistor integration keep getting higher. Nevertheless, the critical drawback of these materials, the mechanical characteristic of lower strength and poor adhesion, become a new concern to the reliability of the device. The interfacial delamination and cracking of copper/low-k interfaces that result from the mismatch of dissimilar material characteristics in elastic modulus, as well as the coefficient of thermal expansion (CTE) after wafer level back end processes, packaging, qualification test, and usage grows into a major reliability concerns of the designers in relative research fields. In this research a mechanics model is proposed to describe the carrier behavior in the silicon under mechanical stress, and the series of the N-type and the P-type doped silicon in the different crystallography orientations under different mechanical stress is discussed. Through the four point bending implement and the dicing direction of the wafer the mechanical stress can be applied in the direction of [100], [110], [010] and [-110]. The results indicate that when the direction of stress coincides with the channel, the tensile/compressive stress can improve the mobility of the N-type/P-type carrier. When stress perpendicular to the channel, the tensile stress enhances the mobility of the P-type carrier and the N-type mobility in the channel of [110] and [-110] direction. But it reduces the mobility of the N-type in the channel of [100] and [010] direction. Moreover since the fracture problem becomes the important issue to the reliability of the device, this research investigates the behavior of the interfacial fracture and the impact of the stress to the reliability in the multilevel interconnection structure based on the global local finite element method. The stable J integral with the appropriate integration path near the crack tip calculated by the finite element simulation was also adopted. The obtained stable J value from the finite element analysis was verified through the analytical solution. The chip with copper/low-k multilevel interconnection using the PBGA package was adopted as the test vehicle in this research. The fracture driving force in the multilevel interconnection structure under the process loading of package level was predicted and compared with the interfacial adhesion of the low-k dielectric materials (2~8 J/m2). The results imply that the fracture driving forces of 1.77 ~ 11.06 J/m2 were calculated when the multilevel interconnection structure experiences the curing process of the epoxy in the PBGA package (from the curing temperature, 180oC to room temperature, 25oC). As the advancement and the expected limitation of the scaling technology, the development of the semiconductor device faces the severe challenge. The impact of the mechanical stress on the new multilevel interconnection structure decreases the reliability of the device hence to reduce the mechanical stress in the multilevel interconnection becomes the urgent issue to keep the low profile/high density device reliable and qualified for using in the electronic product. However, introducing the mechanical stress to the transistor can improve the carrier mobility and it is the important approach to the limitation of the scaling technology. Through the proposed mechanic model, experiment and the established systematical analysis procedure this research investigated the effect of the mechanical stress on the efficiency of the transistor and the reliability of the multilevel interconnection structure. The proposed analysis procedure can also be extended to apply on the other devices or structures.