Abstract
Reliability is an important issue of designing VLSI chips. Many reliability problems are related to switching activity in a circuit. For example, frequent switching of gates can cause severe noise and power, and late switching at primary outputs can induce timing violation and even malfunction. In this thesis we propose theorems related to switching of gates, and based on those theorems, we develop algorithms to solve problems about VLSI reliability. The problems are described as follows. We first focus on the problem of analyzing the maximum instantaneous current (MIC) of a circuit. We propose two different ways to solve this problem. One is to find the worst-case input vectors that activate a tight lower bound of the MIC; one is to estimate a tight upper bound of the MIC in a static way without vectors. Usually static analysis aims at finding a large set of gates switching simultaneously to contribute the MIC. It is well known that signal correlation restricts the simultaneous switching of gates. In this thesis we well study signal correlation and specially, we should be the first to study the signal correlation due to sequential elements. With this knowledge we can derive a tighter upper bound of the MIC than previous methods. Next, about finding the worst-case vectors, the problem can be modeled as the timed ATPG problem. Unlike traditional approaches to developing complex timed ATPG solvers, we propose a method to efficiently construct transition-mode timed characteristic function (TCF), with which the timed ATPG can be reduced to the (conventional) ATPG problem. Then we adopt well-developed (conventional) ATPG or SAT solvers to generate the worst-case vectors. Finally, we propose a novel re-synthesis method for making a circuit become tolerate delay variation, thus improving the timing yield of the circuit. Unlike traditional methods of sacrificing circuit timing, our method adds a small amount of redundant gates to achieve a given degree of delay tolerance. In fact, the experimental results show that on average, our method costs 17% area overhead to improve the timing yield from 77% to 88%.