Abstract
With the advent of deep submicron technology, system-on-chip (SOC) design methodology, heterogeneous cores from different sources can be integrated in a single chip that contains millions of gates. However, the yield of such a large chip is usually too low to be profitable, therefore, yield enhancement is an important issue in SOC product development. Memory cores are among most widely used cores of SOC integration, and an SOC that contains hundreds of SRAM cores is not uncommon today. Memory cores tend to dominate the SOC yield because they usually have a high silicon density and large area characters. Consequently, improving the yield of embedded memory is key in improving chip yield. The many factors of yield enhancement can be divided into some topics. First, memory diagnosis is needed, but the size of test data increases exponentially as the size of memory increases. Thus, fault pattern compression is needed to reduce the size of the test data. Because of the large number of memory cores in a chip, parallel testing and diagnosis is also needed to reduce test time/cost. Secondly, after diagnosis of the memory core, redundancy repair can improve the yield of memory. The repair mechanism has many factors, such as redundancy analysis (RA) algorithm selection, spare element types, and the number of the spare elements. How to select these factors, which affect the efficiency of RA performance and the benefit of the built-in self-repair (BISR) design, needs to predict and evaluate. Timing issues become more important with advance in process technology, but they are difficult to test by built-in self-test mechanisms. Additionally, non-volatile memory requirements have increased recently, and there are many types of non-volatile memories. The testing of the new memory types is also a new challenge. In this paper, we present a few solutions for the important memory issues. First, we propose a method for fail pattern compression based on fail pattern identification, which can compress data up to 6\%. The parallel diagnosis scheme proposed in this paper reduces test/diagnosis time significantly: up to 25\% in the 512$\times$32 memory core. Additionally, an efficient simulator RAISIN is proposed to evaluate the performance and the benefit of the BISR circuit. The delay fault behavior of embedded memory (including SRAM and DRAM) have been analyzed and the efficient test algorithms are also proposed. The proposed new test algorithms do not increase much time complexity. For example, the test algorithm for SRAM is only $10N+6k$ after integrated with March C$-$ test algorithm, which only increases $6k$. Where $k$ is the word count in a row. The magnetic random access memory (MRAM) is considered one of the potential candidates that will replace the current memories (RAM, EEPROM, and flash memory) in the future. In this work we classify and analyze the MRAM defects and their behavior, and propose its fault models. The circuit has been implemented and fabricated with a new 0.18$\mu$m technology. The simulation results regarding the correlation between the defects and conventional fault models show that most defects are covered by the stuck-at fault model. The test data based on the fabricated chips show that the stuck-at faults do cover most of the defects on the chips. However, from the experiment we also have identified two new faults, i.e., the Multi-Victims fault and Kink fault. The proposed approaches resolve the important memory issues efficiently, including test data compression, parallel testing, BISR design and evaluation, timing testing of embedded memories, and MRAM fault modeling and testing.