Abstract
It is common that an SOC contains hundreds or even thousands of heterogeneous embedded memories. Many of these embedded memories have wide data words, leading to a high routing penalty in the BIST circuits. Previous BIST schemes solve the problem by using a serial interface, e.g., a protocol based on the IEEE 1500 architecture or other scan approaches, to reduce routing area overhead. However, serial approaches are slow, and they do not allow at-speed test. In this thesis, we propose a hybrid BIST architecture that effectively reduces the routing penalty of BIST circuit, while allowing at-speed test and diagnosis of memory cores. The test time is close to that of a typical parallel BIST method. Another issue addressed here is that, embedded memory testing of advanced semiconductor products requires expensive Automatic Test Equipments (ATEs), and the cost becomes higher and higher as the manufacturing process technology keeps advancing. To address this issue, the HOY test system which features wireless communication and enhanced embedded test circuits has been developed. HOY reduces test costs dramatically, mainly due to the significant reduction in capital investment, simplification in test infrastructure and flow, increase in parallelism, etc. We first provide the concept, architecture, and test flow for future semiconductor products tested by HOY. We then discuss in detail the testing and diagnosis of embedded memories by HOY. A preliminary demonstration system also has been developed, and the experimental results show that the overall test cost for an industrial case based on 0.18-micron technology can be greatly reduced.