Abstract
This thesis presents the test and yield enhancement associated works for the emerging nonvolatile random access memories (RAMs), specifically the Magnetic Random Access Memory (MRAM) and Resistive Random Access Memory (RRAM). We first address MRAM, which is an emerging nonvolatile memory widely studied for its high speed, high density, and almost unlimited endurance. However, for deep-submicron process technologies, significant variation in MRAM cells’ operating condition results in write failures in cells and reduces the production yield. The Write Disturbance Fault (WDF) due to the operating region shift is a fault model specific to toggle MRAM. March tests have high coverage for conventional RAM faults; however, they do not cover all WDFs. To improve quality of MRAM products, we propose a new test algorithm. The test result of fabricated chips shows the proposed algorithm has higher WDF coverage than traditional March tests. A 1-Mb MRAM prototype chip with the proposed built-in self-test (BIST) circuit has been designed and fabricated using a 0.15m CMOS technology. In addition to test method, we also present a built-in self-configure (BISC) scheme for toggle MRAM to improve the chip yield that may reduce due to variation in the chip’s operating region. The BISC circuit uses a search method to efficiently find and configure each individual chip a suitable operating current through few tester channels. The simulation result shows that the BISC finds the suitable operating point for failed chips in much less time compared with the conventional ATE approach. Production yield thus can be increased while the test cost is greatly reduced. We also discuss RRAM in detail, which is a new type of nonvolatile memory based on the resistive memory device. Over the past decade, many resistive memory devices have been investigated, and some promising ones are identified. Research groups are currently moving from the resistive device development stage to the memory circuit design and implementation stage, hoping to fabricate memory chips that can be deployed in the market in the near future. However, so far the low manufacturing yield is still a major issue for RRAM chips, which will benefit from the introduction of advanced testing methods. In the thesis, we define the Over-Forming (OF) defect and the Read-One-Disturb (R1D) fault specific to RRAM, and then propose a test algorithm to cover these defects and faults in addition to the conventional RAM faults. We also propose a training-based forming method and the built-in self-forming (BISF) circuit. The measurement result shows that the forming method significantly improves the bit yield in much less time than the conventional ATE-based high voltage forming procedure. The proposed test algorithm is applied to a 4-Mb HfO2-based RRAM test chip, and the measurement results show that OF defects and R1D faults do exist in the RRAM chip. We develop a novel squeeze-search scheme to identify the cell resistance. By identifying specific failure patterns and collecting resistance distribution of faulty cells, defects and faults are identified. By our diagnosis method, designers and process engineers will be able to improve the RRAM yield in a more cost-effective way. In addition to the test and diagnosis methodologies, we also present a novel error detection and correction (EDAC) design for RAM. Certain types of NVM have limited endurance, in which the worn cells increase over time in field use. As the number of errors in a data word exceeds the correction capability of the EDAC, operation failure occurs. To extend the lifetime of nonvolatile RAM, we propose an adaptive code rate EDAC scheme. As the defective bits in the memory increases, the codec can be changed to a mode that provides higher correction capability and uses part of user storage for more parity bits, such that the lifetime of the memory is extended. Given a certain reliability level, the proposed design allows more error bits than a conventional EDAC design.