Abstract
Embedded multicore systems are playing increasingly important roles in the design of consumer electronics. Such systems may provide heterogeneous computation power to meet the performance demand of modern applications. As many of the devices are with batteries, the objective of such systems is to optimize both performance and power characteristics of mobile devices. However, currently there are no power metrics supporting popular application design platforms (such as SID), that application developers used to develop their applications. This hinders the ability of application developers to optimize power consumption. In this thesis we present the design and experiments of a SID-based power-aware simulation framework for heterogeneous multicore systems. The proposed power simulator allows a full system simulation with power estimation support for targeting the intellectual properties (IP) used in the platform, including a main processing unit, digital signal processors (DSPs), instruction cache, memory subsystems, interconnections, and DMA. Our power estimation flow includes two phases, IP-level power modeling and power-aware system simulation. The first phase employs PowerMixer{IP} to construct the power model for the processor IP and other major IPs, while the second phase involves a power abstract interpretation method for summarizing the simulation trace, then with a CPE module estimating the power consumption based on the summarized trace information and the input of IP power models. In addition, a Manager component is devised to map each DSP component to a host thread and maintain the access to shared resources. The aim is to maintain the simulation performance as the number of simulated DSP components increases. A power-profiling API is also supported that developers of embedded software can use to tune the granularity of power-profiling for a specific code section of the target application. We demonstrate via case studies and experiments how application developers can use our SID-based power simulator for optimizing the power consumption of their applications. We characterize the power consumption of DSP applications with the DSPstone benchmark and discuss how compiler optimization levels with SIMD intrinsics influence the performance and power consumption. Also, we evaluate a wide range of multicore applications to demonstrate how our power simulator can be used by developers in the optimization process to illustrate different views of power dissipations of applications. Finally, we summarize the major contributions of this thesis as follows: - We propose a SID-based heterogeneous multicore power simulator. We incorporate two processors into the virtual platform to simulate a heterogeneous multicore system: a 32-bit Andes processor and a PAC-DSP. Our design allows simultaneous simulation of multiple PAC-DSP components by using a parallel simulation approach. A PAC Manager component is devised to map each PAC-DSP component to a host thread and maintain the accessing of shared resources. This makes it possible to maintain the simulation performance as the number of simulated PAC-DSP component increases. -We construct the power model of each target system IP includes, the Andes processor, PAC-DSPs, memory subsystem, interconnection, and DMA. Hence our power simulator allows a full system simulation with power estimation support for these targeting IPs that used in the virtual platform. -We also propose a power-profiling API to help developers of embedded software to tune the granularity of power-profiling for a specific code section of the target application. -We evaluate a wide range of DSP and multicore applications that include DSPstone, dual-core FIR application, multicore RMS, and vehicle detection application, in order to demonstrate how application developers can use our power simulator to exploit power optimizations in their applications.