Abstract
In this thesis, we have introduced a new ESSC-TFT structure, which exhibits lower leakage current than that of conventional ES-TFT structure under back light illumination and dark environments, respectively. Although the on-currents may slightly be degraded by the etching process, the on/off current ratio under back light illumination environment is still much larger than the one in the conventional ES-TFT structure. We also provide a possible mechanism and methodology for the worse on-currents of the ESSC-TFTs. Such a new TFT device will enable high-resolution and high-brightness LCDs for next-generation applications; besides, the characteristics of lower leakage under dark environment also make ESSC-TFT device a suitable candidate for X-ray image-sensor applications. Two types of dual-gate TFTs have shown the different electrical characteristics; the on-currents of type B TFTs are correlated to the lengths of ITO top gate. On the contrary, the type A devices nearly keep a certain quantity of on currents regardless of the size of ITO length. For the off state, the type A devices exhibit higher leakage currents than both type B devices and control samples, while the type B devices show almost the same leakage quantity with the control samples. This is due to the high impedance of intrinsic a-Si:H in the region between the ITO gate and source/drain contact. We also first observed that both type A and type B dual-gate TFTs show lower photo-leakage current than conventional TFTs and applied a proper mechanisms and explanation to this phenomenon. We also try to develop a measurement methodology to obtain the real TFT parasitic capacitance, and a simulation methodology is also introduced to verify our measurement results here. By using this measurement method, the conventional dual-gate TFTs are realized not suitable for LCD fabrication due to the inevitable increased CGS. The asymmetric dual-gate TFT is thereby introduced to overcome the shortcoming. High performance 1.8” asymmetric dual-gate TFT-LCDs with 114 dpi and 160×128 resolution are also demonstrated here. A transient measurement method to estimate the real performance of a a-Si:H TFT in a GOA (Gate driver on array) circuits has been described. The conventional DC measurement is insufficient to be used to describe the AC driving behaviors of a a-Si:H TFT due to the long DC measurement time can heat up the device and obtain the inaccurate results for circuit simulations. In this thesis, we also found that Larger channel width, shorter channel length, smaller device area and higher driving bias can also enhance the self-heating effect in a-Si:H TFTs by transient measurements. Two mechanisms of threshold voltage of the a-Si:H TFT metastability are introduced, and the stretched exponential model is used to extract the critical parameters of the defect creation. The point defect creation is proved to be reversible by the annealing process with a certain relaxation time by a series bias stress experiments tested on numbers of three-layer capacitors. The carrier trapping in insulator has also been observed with high voltage bias above 60V, which the capacitor cannot be recovered to its initial state. Furthermore, the humidity effect on a a-Si:H TFT has also been observed. The leakage current in a-Si:H TFTs increases exponentially and saturated at high relative humidity. This confirm that the leakage current in a-Si:H TFTs is strongly affected by the water molecules on the top passivation layer. The water molecules act as a positive charges as can be verified by the dual-gate a-Si:H TFT with various top gate biases. The leakage current of the a-Si:H TFTs with photo-illumination and humidity environment is also observed in this thesis.