Abstract
According to International Technology Roadmap for Semiconductor (ITRS), logic and memory devices are being continuously scaled down to reduce the area of the chip and the cost. However, traditional dielectric material SiO2 will face the physical limitation of nano device – large leakage current and device will fail. This scaling issue is a formidable challenge especially for emerging system-on-chip (SoC) integrated circuit designs in which a continuously scaling of gate dielectrics for complementary metal oxide semiconductor and tunneling oxide for non-volatile memory is needed to have high density and low operating voltage. To meet this requirement, high dielectric constant (k) materials provide the only solution since decreasing the dielectric thickness (t) degrades both the leakage current and devices performance. In recent years, logic and memory devices applying high dielectric constant (k) materials become one of the most important researches in the semiconductor industry. In this dissertation, we will investigate the application of several high-k dielectric materials for metal-gate/high-k CMOSFETs、MIM Analog-RF/DRAM Capacitors and MONOS non-volatile memory (NVM). First of all, we demonstrate low Vt of 0.12 and -0.17 V, in dual [TaN-TaN/Ir]/LaTiO n- and p-MOS at 0.63 and 0.66 nm EOT, with good 0.8 MV/cm mobility of 126 and 54 cm2/Vs. This was achieved using Ni-induced solid-phase diffusion to lower high-k interface reaction, with simple self-aligned and gate-first process, compatible with current VLSI. Next, for metal-insulator-metal (MIM) capacitors using high-k dielectric materials for Analog-RF/DRAM, we have fabricated high-k Ni/TiO2/ZrO2/TiN metal-insulator-metal (MIM) capacitors. A low leakage current of 8x10-8 A/cm2 at 125oC was obtained with a high 38 fF/um2 capacitance density and better than ZrO2 MIM capacitors. The excellent device performance is due to the lower electric field in 9.5 nm thick TiO2/ZrO2 devices to decrease leakage current and the higher k of 58 for TiO2 than ZrO2 to preserve the high capacitance density. We also studied the stress reliability of high-k Ni/TiO2/ZrO2/TiN metal-insulator-metal capacitors under constant-voltage stress. The increasing TiO2 thickness on ZrO2 improves the 125oC leakage current, capacitance variation (delta-C/C), and the long term reliability. Finally, we also applied high-k dielectric materials for non-volatile memory. We report a novel charge-tapping-engineered flash (CTEF) non-volatile memory with very thin 5 nm Si3N4 that has a large 5.6 V initial memory window and 3.8 V 10-year extrapolated retention window at 150oC and under a fast 100 us and +16/-16 V program/erase. These were achieved using shallow- and deep -energy Si3N4-HfON trapping layers that are much better than the memory device characteristics for the similar structure without the extra 0.9 nm EOT HfON layer.