Abstract
Over the past 10 years, the dimension of NAND flash cell has decreased dramatically, from 130nm to middle-1Xnm. As technology nodes advance, various scaling barriers appear, and minor effects become increasingly problematic. Therefore, scaling conventional floating gate technology is very difficult due to physical and electrical limitations. This dissertation proposes some feasibility of fabricating optimized processes on 50-nm NAND Flash technology. First, a flat-bottom Control Gate (CG) with a raised STI has been developed to maintain adequate reliability distance against stresses from cycling, as well as filling in the small Floating Gate (FG) to FG spacing. Thus, the proposed flat-bottom CG structure and process are the most promising solution for advanced Self-Aligned shallow trench isolation (SA-STI) structure exceeding 50 nm. Second, the “redirection programming electron” Inter-Poly Dielectric (IPD) leakage in the traditional SA-STI structure presented here for the first time and redirection IPD leakage current are determined, these should be considered new phenomena. The design of NAND Flash structure should be optimized by a smaller CG fringing E-field effect and special IPD engineering for this unanticipated leakage current when scaling future NAND Flash. Third, this dissertation demonstrates the feasibility of the degradation model of data retention on NAND Flash memory as the bottom poly oxide (BPO) is scaled down. The proposed solution, involving an optimized IPD film scheme with FG top nitridation, solves the “FG charge loss” problem and eliminates “trapped electrons back-tunneling” from the IPD. Finally, the degradation model of the passivation process on a FG type NAND Flash memory is demonstrated. The water (moisture) diffusion model explains all degradation phenomena and observations explain why post metallization anneal (PMA) should be arranged before the deposition of the top P-SiN or the coating of the top metal with Polymide (PI). This dissertation contributes significantly to efforts to improve the endurance and retention of FG-type NAND Flash memory by optimizing the passivation process flow and film scheme. In summary, this dissertation provides some design considerations for cell structure and promising solutions to continue miniaturizing the technology with the same reliability characteristics.