Abstract
In this thesis, I first introduce the market, the applications and the fundamental circuit architecture development of CMOS image sensor (CIS). And then I present my first IC work: “a low-power high dynamic range smart CIS”, which includes the research motivations and target applications, the key features, circuit descriptions and the measurements with summary. Next I demonstrate my second IC work: “a high-speed digital time delay integration (TDI) CIS”, which includes background, specifications, TDI concept, circuit descriptions and the measurements with summary. At the end of this thesis, I conclude these two works and explain the future works. A smart image sensor is designed with multiple operation modes including edge extraction (EE), multi-point tracking (MPT), and high-dynamic-range (HDR) imaging for wireless sensor nodes in internet-of-things (IoT) applications. The pixel consists of a 0.5 V operated pulse-width-modulation (PWM) sensor for achieving high dynamic range (HDR) response and low fixed pattern noise. Array-level image signal processing is implemented by using a local inter-pixel feedback network, in-pixel low power dynamic logics, and a corresponding peripheral with an event-driven hand-shaking readout. A prototype chip with a 64 × 64 CIS array is designed and fabricated in TSMC 0.18-μm CIS technology. In MPT mode, the measured tracking speed is 14.28 kfps with an error of 0.36 pixels and a tracking capability up to four-point. In HDR imaging mode, the achieved dynamic range is 96.7 dB. A 512-column high-speed linear scan image sensor is designed with 32-stage digital time-delay-integration operation. A signal processing architecture consists of analog front end (AFE), analog-to-digital converters (ADC), and digital accumulators (DA) are designed with optimization of timing, area, and power efficiency. An 8-column-shared 10b SAR ADC with data prediction switching (DPS) technique and 11b DA are proposed to achieve a data depth of 15 bit after 32-stage TDI. The achieved signal-to-noise ratio (SNR) boost is 14.84dB after 32-stage TDI operation. The proposed linear TDI sensor is implemented in 0.11-μm TSMC backside illumination (BSI) CIS technology with a line time of 104μs, a pixel pitch of 7.5μm, and a power consumption of 153.2μW/column. Compare with the state-of-the-art designs, the proposed image sensors are more competitive in system optimization.