Abstract
To sustain CMOS transistor continuously scaling, high-k and metal gate technology has become the foundation of logic CMOS technology. Because of the direct tunneling effect, a high gate leakage will be induced in the conventional Poly/SiON gate with a very thin SiON dielectric. Besides, the poly depletion effect also limits Tox_inv for further scaling. Furthermore, the p-type effect work function of a metal gate electrode is easily degraded to Si middle band gap after high temperature activation steps. To overcome the drawback, in this thesis, we study the use of post dielectric annealing, Al2O3 cap layer, F or Al implantation to modulate work functions of gate metals to meet the p-type MOSFET requirements. By integrating F incorporation and Al implantation in gate first scheme, valence band edge effect work function has been successfully achieved with slightly Jg degradation. Besides, the equivalent oxide thickness (EOT) scaling capability is also restricted in gate first scheme with high temperature thermal budget. For future device applications, a gate lat scheme suppressing high temperature steps is proposed. Experimental results of I/V, C/V and energy dispersive X-ray spectroscopy (EDS) had evidenced the proposal is available for nano scale p-type MOSFET applications. Valence band edge effective work function and better EOT scaling capability have been demonstrated. By introducing suitable low temperature O2 post metal annealing, work function can be further improved without Jg degradation and EOT penalties. Furthermore, EDS depth profiling through metal gate stacks also revealed that the oxygen content controlled the p-type metal gate work function.