Abstract
This dissertation proposes a new fully CMOS logic compatible Multi-Time Programmable (MTP) memory cell for serving the high density and low cost requirements of logic non-volatile memory applications. The MTP cell firstly adopts a novel Contact Coupling Gate (CCG) structure as an additional control gate in highly efficient operations and high density memory applications. The new CCG structure is composed of a contact electrode and RPO oxide, which play the roles of control gate and inter-poly oxide in a conventional Stack Gate Flash. The new and small CCG MTP cell has been characterized and proposed to replace the current MTP solution with a larger area or complex or incompatible processes. In terms of the feasibility study, a dense-pitched 2Kbit CCG memory chip has also been successfully demonstrated on a pure 0.18μm CMOS logic process without extra masking or process steps. With the aid of the CCG, a highly efficiently CHE program and FN tunneling erase are achieved and the cell still retains its high cycling endurance and superior data retention. Since the cell size of the CCG MTP can be reduced to 0.808μm2 by a 0.18um CMOS logic design rule, this makes it very suitable for a high density application with fully CMOS logic compatible processes. In summary, with its high performance, low cost, and simple fabrication, the proposed CCG MTP technology is one of the most promising solutions in advanced logic NVM applications.