Abstract
The Magnetic Random Access Memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM is fast and does not need a high supply voltage for Read/Write operations, and is compatible with the CMOS technology. It can also endure almost unlimited Read/Write cycles. These combined advantages of RAM and flash memory make it a potential choice for SOC. In this thesis, we present the Write Disturbance Fault (WDF) model for MRAM, i.e., a fault that affects the data stored in the MRAM cells due to excessive magnetic field during the Write operation. March tests have high coverage for conventional RAM faults; however, they do not detect all WDFs. To improve quality and yield of MRAM, we propose a new test algorithm to detect WDF for MRAM in this thesis. The proposed test algorithm is a March-based one, i.e., it has linear time complexity and can easily be implemented with built-in self-test (BIST). We then present an MRAM fault simulator called RAMSES-M, based on which we derive the shortest test for the proposed WDF model. Furthermore, to enhance the ability of diagnosis, we propose an adaptive diagnosis algorithm (ADA) that can efficiently identify the WDF for MRAM. However, the proposed test method can evaluate the process stability and uniformity using logical test method. We collaborated with EOL to construct the SPICE macro model for the magnetic tunneling junction (MTJ) device of the toggle MRAM to obtain circuit simulation results. Additionally, we present a built-in self-test (BIST) circuit that supports the proposed WDF diagnosis test method. We propose the BIST scheme based on the Decision Write mechanism of the toggle MRAM to reduce total test time. Experimental results show that the fault coverage of proposed test algorithm is higher than that of traditional March test algorithms. Also, circuit simulation result justifies that the adaptive diagnosis algorithm is useful for diagnosis of a WDF cell. The proposed BIST circuit has only 0.05% of hardware overhead for a 1-Mbit MRAM, and test time is further shortened for the toggle MRAM. Furthermore, the proposed WDF model is justified by chip measurement results. Finally, specific MRAM fault behavior and test issues are discussed.