Abstract
Low power applications are a major trend in today’s portable SoCs (System-On-Chip). Many SoCs utilize low voltage operation to reduce leakage power and to lengthen battery life. The yield of traditional SRAM has faced serious limitations in low operational voltage (VDDmin) due to random doping fluctuation and lithographic dependent threshold voltage (VTH) variations in nanometer technologies. The variations lower the read stability and write margins, thereby inducing read disturb failure or write failure when low voltage operation. In order to meet low voltage requirements, we propose A) Differential data aware power-supplied (D2AP) 8T-SRAM, B) Zigzag 8T SRAM (Z8T) and C) Write assist 8T cell (WA8T) for DP-SRAM to suppress write disturbance. The proposed D2AP 8T-SRAM cell applies differential data-aware-supplied voltages to its cross-coupled inverters to increase both stability margins for write and half-select accesses. A boosted bit-line scheme also improves the read cell current. Two 39Kb SRAM macros were fabricated on the same testchip with 45nm and 40nm processes. The measured VDDmin for the D2AP-8T macro is 240mV-200mV lower than that of the conventional 8T macro. The proposed Z8T SRAM uses only 1T for each decoupled read-port, faster 2T differential sensing (D2S) can be implemented within the same area as the decoupled single-ended 8T (DS8T). Z8T cell enables much faster R/W speed at VDDmin than that of DS8T. For the same VDDmin/speed, Z8T reduces the cell area by 15%. The Z8T 32Kb macro is 14% smaller area and 53% faster than DS8T cells. The measured VDDmin for a 65nm 256-row 32Kb and a 32-row 4Kb macro are 430mV and 250mV respectively. The measured VDDmin for a 90nm 256-row 64Kb macro is 230mV. The proposed WA8T suppress the write disturbance for DP-SRAM to achieve a lower VDDmin with low area overhead and power consumption. We fabricated a 1Mb DP-SRAM with WA8T testchip using a 40nm CMOS process. The proposed WA8T improves VDDmin to achieve 120mV improvement with less than 1% area overhead.