Abstract
With the advances of VLSI design technology, yield loss, manufacturing cost, and reliability are more and more important. To tackle these issues, the yield improvement, cost reduction, and reliability mechanisms methodologies are required. In this dissertation, X-identi cation method, re-use methodology, and architecture of fault tolerance are proposed to achieve these goals. First, to reduce the yield loss in high-performance design, a physical-location-aware X-identi cation method is presented. To guarantee that an application speci c integrated circuit (ASIC) meets its timing requirement, at speed scan testing becomes an indispensable procedure for verifying the performance of ASIC. However, at-speed scan test su ers the test-induced yield loss. Because the switching-activity in test mode is much higher than that in normal mode, the switching-induced large current drawn causes severe IR drop and increases gate delay. X- lling is the most commonly used technique to reduce IR-drop e ffect during at-speed test. However, the eff ectiveness of X- lling depends on the number and the characteristic of X-bit distribution. In this dissertation, we propose a physical-location-aware X-identi cation which re-distributes X-bits so that the maximum switching-activity is guaranteed to be reduced after X- lling. We estimate IR-drop using RedHawk tool and the experimental results on ITC'99 show that our method has an average of 9.42% more reduction of maximum IR-drop as compared to a previous work which re-distributes X-bits evenly in all test vectors. Second, a clock tree algorithm with methodology of reuse in 3-D IC is proposed. IP reuse methodology has been used extensively in SoC (System on Chip) design. In this reuse methodology, while design and implementation cost is saved, manufacturing cost is not. To further reduce the cost, this reuse concept has been proposed at mask and die level in three-dimension integrated circuit (3D IC). In order to achieve manufacturing reuse, in this dissertation, we propose a new methodology to design a global clock tree in 3D IC. The objective is to extend an existing clock tree in 2D IC to 3D IC taking into consideration the wirelength, clock skew and the number of TSVs. Compared with NNG-based method, our proposed method reduces the wirelength of the new die and the skew of the global 3D clock tree, on an average, 76:92% and 5:85%, respectively. Finally, an architecture of TSV recovery by using test elevator TSV is proposed. In order to increase the yield of 3-D IC, fault-tolerance technique to recover failed TSV is essential. In this dissertation, an architecture of TSV recovery by using test elevator TSV is proposed. With the architecture, no spare TSV is required to be inserted in advance. Hence, no extra area incurs. TSV assignment algorithm based on min-cost maximum-flow is proposed taking into consideration the locations of functional TSV as well as test TSV, so that the total Half-Perimeter Wire Length (HPWL) of a 3-D IC design is e ectively reduced. Experimental results show that the total wirelength of 3-D IC testing is improved by 20% in average compared to that of spare TSV approach.