Abstract
Content addressable memories (CAMs) support a wide range of computing and communications applications. In this thesis, we propose a low-power CAM design, which is suitable for implementing a high-performance LZ77-based data compressor. By shutting down the power for unnecessary comparisons between the CAM words and the input symbol, the proposed CAM architecture consumes much lower power than the conventional ones without noticeable performance penalty. Our approach also can be applied to general-purpose CAMs which use the valid bits, so far as the proposed design techniques are adopted. Testing for CAMs are also considered in this thesis. We consider the fault models based on physical defects, such as shorts between two circuit nodes and transistor stuck-on and stuck-open faults. Several effective functional tests for CAMs are presented accordignly. In order to make our approach suited to various application-specific CAMs, the tests require only three fundamental types of operation (i.e., write, erase, and compare), and the test results can be observed entirely from the single-bit Hit output. A complete, compact test requires only 2N + 3w + 2 compare operations and 8N write operations to cover the functional fault models discussed, where N is the number of words and w is the word length. The test has low complexity and is suitable for modern high-density and large-capacity CAMs. In this thesis, we also present practical realization of multiple-input exclusive-or (EXOR) circuits, which is similar to the CAM's compare mechanism and useful in many applications, such as parity generator, checker, and Exclusive-OR Sum-of-Product (ESOP) circuits, Two kinds of multiple-input EXOR circuit structures are presented, which are smaller, faster, and more power-saving than those formed by simply connecting two-input EXOR gates in a conventional way. The reduction in area and power make them attractive for low-power required applications such as mobile computing and wireless communications.