Abstract
In developing an accurate lifetime prediction model for post-cycling data retention failure rate of split-gate flash memories, a floating-gate potential extraction method from the measured bit-cell-current data is proposed. Stress induced leakage current through the coupling oxide caused by source side channel hot electron injection during program operation is the major cause for post-cycling data retention failure bits. Considering charge conservation and trap-assist-tunnelling (TAT) leakage current, the charge gain behavior under low temperature bake is modelled and the failure rate under various measured conditions can be predicted precisely. We have found that data retention lifetime decrease as P/E cycling increases, while failing bits increase with numbers of P/E cycling. In addition, in order to develop a fast statistical testing methodology to predict post-cycling low-temperature-data-retention (LTDR) lifetime of split-gate flash memories, word-line stress is used to accelerate the charge gain effect responsible for bit-cell-current (BCC) reduction among the tail-bits. To find out the voltage dependence on data retention lifetime, various word-line stress voltages are performed to enhance the charge gain effect of the erased-state cells. At an accelerated state, word-line stress lifetime tests can be completed within a much shorter test period and still provide accurate lifetime prediction for embedded flash memory products. Based on the reliability statistics and TAT-related lifetime model introduced in chapter three, the thermal-acceleration reliability statistics, gate-oxide thickness dependence, and device area (cells per array/chip) dependence on data-retention lifetime of high-reliability flash memory products are comprehensively discussed. According to the gate-oxide dependence on data-retention lifetime, a gate-oxide thickness of 10nm is required to achieve a single-ppm parts-level failure rate in fifteen years for high-reliability flash memory products.