Abstract
Failure analysis (FA) is one of the key competencies and enables reasonable time-to-market, resulting in higher profit than other competitors. Conventional FA for memories based on bitmaps and the experiences of the FA engineer is time consuming and hard to meet the increasing time-to-volume pressure on semiconductor products. To reach a profitable yield level rapidly in new development flow demands an efficient and automatic FA methodology. An advanced memory failure analysis framework is proposed---the Failure Analyzer for MEmories (FAME), to facilitate the defect diagnosis and yield ramp-up in system-on-chip (SOC) product development. Our FAME integrates the Memory Error Catch and Analysis (MECA) system and Memory Defect Diagnostics (MDD) system. The fault-type based diagnostics approach used by MECA can improve the efficiency of the test and diagnostic algorithms. Furthermore, we also developed a systematic diagnosis approach based on the novel fault-pattern approach. It is used in the MDD system to improve the defect identification capability. Defect diagnosis and FA can be performed automatically by using the MDD, reducing the time in yield improvement. FAME also comes with a powerful viewer for inspecting the failure patterns and fault patterns. It provides an easy way to narrow down the potential cause of failures and identify possible defects. We also demonstrate the ability of parametric testing for defect-level diagnostics with proper design-for-test support in memories. Combining the proposed framework and parametric testing can achieve excellent diagnostic results. An experiment has been done on an industrial case, demonstrating very accurate results in a much shorter time as compared with the conventional way. The main benefit of FAME is thus an automatic methodology and procedure for accelerating FA and yield optimization for semiconductor memories.