Abstract
Silicon VLSI technology, providing chips consisting of milti-million of transistors, promises new level of system integration onto a single chip. With the rapid growth of network and communication applications, digital signal processor (DSP) for communications, and memory cores of various architectures, will play important roles in many System-on-Chip (SoC) applications in the future. A Communications Processor (COP) core is a processor magacell for communication applications, i.e., source coding, channel coding and cryptography, etc. In this thesis, design and test strategies of processor and memory cores for communications SoC environment are presented. An improved architecture of error-correction coding is developed, which is suitable for the datapath and software implementation in COP. Additionally, since Galois Field (GF) arithmetic units are the key components of the communication and network processing for error-correction coding and cryptography systems, a GF inversion algorithm of high testability and scalability is illustrated. The easily testable GF inverter, together with the highly-testable GF multiplier design previous proposed, will reduce the test effort of the datapath units and facilitate the test integration of COP system. COP processes a large amount of digital data with the help of various memory cores, including SRAMs, DRAMs and register files, etc. Consequently, a Built-In Self-Test (BIST) design for embedded DRAM is described. Based on the BIST architecture, a framework of the memory BIST compiler called BRAINS is developed for common SRAMs and DRAMs, with the capability of future extension for new memory architectures.