Abstract
As the dimension of integrated circuits and semiconductor technology continues shrinking, the resistance-capacitance delay induced by metal line and inter-metal dielectrics has become a critical issue. To improve the circuit operation speed, copper interconnects and low-k dielectrics materials are introduced to reduce metal wiring resistance and parasitic capacitance. However, copper stress migration (SM or stress-induce voiding (SIV)) and time-dependent dielectrics breakdown (TDDB) of low-k dielectrics become significant reliability concerns. In this work, Cu SM in terms of different Cu/low-k microstructure scenarios are modeled to understand the voiding evolution with the assistance of finite element analysis (FEA) and explore their dependence with SM susceptibility. Microstructure effects with and without redundant via are also simulated to evaluate their impacts on improving SIV immunity. For a new SM failure mode occurred at narrow metal finger connected with wide lead, failure rate and its geometric dependency are also studied. A computing model considering migration path and hydrostatic stress gradient is used to study the vacancy migration tendency and the influence from effective volume in different geometric scenarios. Another FEA model is also established to simulate the resistance change in terms of void location, void morphology and interconnect scenarios. Regarding low-k dielectrics TDDB, temperature-dependent leakage, Schottky emission and Poole-Frenkel emission of dense and porous low-k SiCO dielectrics are respectively analyzed. TDDB study in low electrical field verifies a square root of electrical field behaviour for low-k SiCO lifetime prediction. Additionally, TDDB with regard to lifetime, failure mechanism, thermal activation energy and length scaling effect are also investigated. As a result, Cu SM and low-k SiCO dielectrics TDDB are characterized for the reference of improvement and risk assessment in advanced semiconductor process.