Abstract
This study presents a novel fabrication process of post-CMOS (complementary metal oxide semiconductor) with the chemical plasma etching. To release the CMOS microstructures, the shorter mean free path to increase lateral etching can be employed in the rough vacuum. The etching profile trends isotropy and the capability of lateral etching are controlled by pressure of the chamber. In addition, the chemical plasma etching can release silicon dioxide under the mask. This approach can fabricate symmetric geometry in the vertical direction to decrease the effect of CMOS–MEMS residual stress. Moreover, the thin single metal layer structures also can be fabricated by chemical plasma etching such as micro-spring. It has the characteristics of the lower spring constant to increase the displacement of the proof mass. Thus, the sensitivity can be further improved. A parallel-plate capacitive vertical CMOS accelerometer is demonstrated in this new concept of post-CMOS process. Based on this approach, the measured results show the residual stresses effect can be minimized in CMOS multilayer microstructures, and furthermore the curl-up effect of flat-plane is less than 2 µm across the 500 μm × 500 μm area. The sensitivity of the vertical CMOS accelerometer is about 3.2 mV/g, and total noise floor is 10 μV / √Hz.